LH28F800BVE-BV85 Sharp Electronics, LH28F800BVE-BV85 Datasheet - Page 14

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LH28F800BVE-BV85

Manufacturer Part Number
LH28F800BVE-BV85
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F800BVE-BV85

Cell Type
NOR
Density
8Mb
Access Time (max)
85ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
20/19Bit
Operating Supply Voltage (typ)
5V
Operating Temp Range
0C to 70C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
65mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant
NOTES:
1. BUS operations are defined in Table 3.1 and Table 3.2.
2. X=Any valid address within the device.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 for
5. If the block is boot block, WP# must be at V
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Word/Byte Write
Block Erase and Word/Byte
Write Suspend
Block Erase and Word/Byte
Write Resume
sharp
IA=Identifier Code Address: see Figure 4. A
BA=Address within the block being erased. The each block can select by the address pin A
WA=Address of memory location to be written.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID=Data read from identifier codes.
read identifier code data.
operations. Attempts to issue a block erase or word/byte write to a boot block while WP# is V
used.
Command
Bus Cycles
Req’d.
≥2
1
2
1
2
2
1
1
Table 4. Command Definitions
-1
Notes
5,6
set to V
4
5
5
5
IH
LHF80V35
or RP# must be at V
IL
Oper
Write
Write
Write
Write
Write
Write
Write
Write
or V
(1)
IH
First Bus Cycle
in Byte Mode (BYTE#=V
Addr
WA
BA
X
X
X
X
X
X
(2)
(7)
HH
Data
40H or
to enable block erase or word/byte write
D0H
FFH
B0H
90H
70H
50H
20H
10H
(3)
Oper
IL
Write
Write
18
Read
Read
).
through A
IH
(1)
Second Bus Cycle
or RP# is V
Addr
WA
BA
12
IA
X
combination.
(2)
IH
.
Data
SRD
D0H
Rev. 1.1
WD
ID
(3)
11

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