LH28F800BJHE-PBTL90 Sharp Electronics, LH28F800BJHE-PBTL90 Datasheet
LH28F800BJHE-PBTL90
Specifications of LH28F800BJHE-PBTL90
Related parts for LH28F800BJHE-PBTL90
LH28F800BJHE-PBTL90 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F800BJHE-PBTL90 8M (512 KB × 1MB × 8) ® Flash Memory (Model No.: LHF80J05) Spec No.: EL152049 Issue Date: February 14, 2003 Integrated Circuits Group ...
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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please ...
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INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 1.3 Product Description...................................................... 4 1.3.1 Package Pinout ....................................................... 4 1.3.2 Block Organization................................................. 4 2 PRINCIPLES OF OPERATION........................................ 7 2.1 Data Protection............................................................. 8 3 BUS OPERATION ............................................................ 8 3.1 ...
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... These alternatives give designers ultimate control of their code security needs. The product is manufactured on SHARP’s 0.25µm ETOX 48-lead TSOP, ideal for board constrained applications. *ETOX is a trademark of Intel Corporation. LHF80J05 LH28F800BJHE-PBTL90 ■ Enhanced Automated Suspend Options Word/Byte Write Suspend to Read Block Erase Suspend to Word/Byte Write Block Erase Suspend to Read ■ ...
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... INTRODUCTION This datasheet contains the product specifications. Section 1 provides a flash memory overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Features Key enhancements of the product are: •Single low voltage operation •Low power consumption •Enhanced Suspend Capabilities • ...
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The access time is 90ns (t ) over the operating AVQV temperature range (-40°C to +85°C) and V voltage range of 2.7V-3.6V. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode ...
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Input A -A Decoder -1 18 Buffer Address Decoder Latch Address Counter ...
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... CCW may be connected to 12V±0.3V for a total of 80 hours maximum. DEVICE POWER SUPPLY: Do not float any power pins. With V V SUPPLY the flash memory are inhibited. Device operations at invalid V CC Characteristics) produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. ...
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... Interface software that initiates and polls progress of block erase, full chip erase, word/byte write and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase ...
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... Refer to Table 5 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes ...
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Read Identifier Codes The read identifier codes operation manufacturer code, device code, block lock configuration codes for each block and the permanent lock configuration code (see Figure 4). Using the manufacturer and device codes, the system CPU can ...
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Write Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When the CUI additionally controls block CCW CCWH1/2 erase, full ...
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Bus Cycles Command Req’d. Read Array/Reset 1 ≥2 Read Identifier Codes Read Status Register 2 Clear Status Register 1 Block Erase 2 Full Chip Erase 2 Word/Byte Write 2 Block Erase and Word/Byte 1 Write Suspend Block Erase and ...
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Read Array Command Upon initial device power-up and after exit from reset mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
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Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to V ...
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Set Block and Permanent Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and WP# pin. The block lock-bits and WP# pin gates program and erase operations ...
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... If OTP write is attempted when the OTP Lock-bit is set, SR.1 and SR.4 is set to "1". 4.13 Block Locking by the WP# This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary ...
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Permanent Operation V RP# CCW Lock-Bit Block Erase ≤V X CCWLK or >V V CCWLK IL Word/Byte V IH Write ≤V Full Chip X CCWLK Erase >V V CCWLK ≤V Set Block X CCWLK Lock-Bit >V ...
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WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H Write Word/Byte Data and Address Read Status Register No Suspend 0 SR.7= Word/Byte Write 1 Full Status Check if Desired Word/Byte Write Complete FULL STATUS CHECK ...
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Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Word/Byte Write Read Word/Byte Write ? Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Block Erase Resumed Figure 9. ...
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Start Write B0H Read Status Register 0 SR. Word/Byte Write Completed SR.2= 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word/Byte Write Resumed Read Array Data Figure 10. Word/Byte Write Suspend/Resume ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write 01H/F1H, Block/Device Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write C0H Write Data and Address Read Status Register 0 SR.7= 1 Full Status Check if Desired OTP Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 ...
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... PC board trace inductance. 5.4 V Trace on Printed Circuit Boards CCW Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V CCW supplies the memory cell current for word/byte writing and block erasing ...
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... For the lockout voltage, refer to the specification. (See chapter 6.2.3.) 3) Data protection through RP# When the RP# is kept low during read mode, the flash memory will be reset mode, then write protecting all blocks. When the RP# is kept low during power up and ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration .............-40°C to +85°C Storage Temperature During under Bias ............................... -40°C to +85°C During non Bias ................................ -65°C to ...
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AC Input/Output Test Conditions 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V. Input rise and fall times ...
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DC Characteristics Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Auto Power-Save Current CCAS Reset Power-Down Current CCD Read Current ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout during Normal CCWLK CCW Operations V V ...
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AC Characteristics - Read-Only Operations Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV ...
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Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z ...
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AC Characteristics - Write Operations Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP#V Setup to ...
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V IH ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR. ("0") ...
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Alternative CE#-Controlled Writes Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP#V Setup to CE# Going ...
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V IH ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#( High Z ("1") RY/BY#(R) (SR. ("0") V ...
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Reset Operations High Z ("1") RY/BY#(R) (SR. ("0" RP#( High Z ("1") RY/BY#(R) (SR. ("0" RP#( (B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or ...
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Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Performance Sym. Parameter t Word Write Time 32K word Block WHQV1 t 4K word Block EHQV1 Byte Write Time 64K byte Block 8K byte Block Block Write Time ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory RP#, V AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...