LH28F160S3HT-L10 Sharp Electronics, LH28F160S3HT-L10 Datasheet
LH28F160S3HT-L10
Specifications of LH28F160S3HT-L10
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LH28F160S3HT-L10 Summary of contents
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... P S RODUCT PECIFICATIONS LH28F160S3HNS-L10 Flash Memory 16M (2M×8/1Mx16) Issue Date: February 5, 2001 ® (Model No.: LHF16KAS) Spec No.: EL131052 Integrated Circuits Group ...
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Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ●When using the products covered herein, please ...
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INTRODUCTION ...................................................... 3 1.1 Product Overview ................................................ 3 2 PRINCIPLES OF OPERATION ................................ 6 2.1 Data Protection ................................................... 7 3 BUS OPERATION.................................................... 7 3.1 Read ................................................................... 7 3.2 Output Disable .................................................... 7 3.3 Standby ............................................................... 7 3.4 Deep ...
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... SIMMs and memory cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160S3HNS-L10 offers three levels of protection: absolute protection with V GND, selective hardware block locking, or flexible software block locking ...
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... Word/byte CC PP LHF16KAS write suspend mode enables the system to read data or execute code from any other flash memory array location. Individual block locking uses a combination of bits and WP#, Thirty-two block lock-bits, to lock and unlock blocks. Block lock-bits gate block erase, full chip erase and (multi) word/byte write operations ...
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Input Buffer Address Latch Address Counter ...
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... SUPPLY V to the new voltage. Do not float any power pins. With the flash memory are inhibited. Device operations at invalid V Characteristics) produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins CONNECT: Lead is not internal connected; it may be driven or floated. ...
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... Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Write suspend allows system software to suspend a (multi) word/byte write to read data from any other flash memory array location. LHF16KAS 1FFFFF 1F0000 ...
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... Time t goes to logic-high (V be written. As with any automated device important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash #), OE#, WE#, 1 memory. Automated flash memories provide status information when accessed during block erase, full ...
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... Query Operation The query operation outputs the query structure. Query database is stored in the 48Byte ROM. Query structure allows system software to gain critical information for controlling the flash component. Query structure are always presented on the lowest- order data output (DQ 3.7 Write Writing commands to the CUI enable reading of device data and identifier codes ...
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Mode Notes Read 1,2,3,9 Output Disable 3 Standby 3 Deep Power-Down 4 Read Identifier 9 Codes Query 9 Write 3,7,8,9 Mode Notes Read 1,2,3,9 Output Disable 3 Standby 3 Deep Power-Down 4 Read Identifier 9 Codes Query 9 Write ...
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Command Read Array/Reset Read Identifier Codes Query Read Status Register Clear Status Register Block Erase Setup/Confirm Full Chip Erase Setup/Confirm Word/Byte Write Setup/Write Alternate Word/Byte Write Setup/Write Multi Word/Byte Write Setup/Confirm Block Erase and (Multi) Word/byte Write Suspend Confirm ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads ...
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... Query database can be read by writing Query command (98H). Following the command write, read cycle from address shown in Table 7~11 retrieve the critical information to write, erase and otherwise control the flash component. A address is ignored when X8 mode (BYTE#=V Query data are always presented on the low-byte data output (DQ -DQ ) ...
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... CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported. Offset Length (Word Address) 10H,11H,12H 03H 13H,14H 02H ...
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... SCS OEM Specific Extended Query Table Certain flash features and commands may be optional in a vendor-specific algorithm specification. The optional vendor-specific Query table(s) may be used to specify this and other types of information. These structures are defined solely by the flash vendor(s). ...
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Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence appropriate sequencing and an ...
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... SR.4 and SR.5 should be cleared before issuing multi word/byte write command multi word/byte write command is attempted past an erase block boundary, the device will write the data to Flash Array erase block boundary and then stop writing. Status register bits SR.4 and SR.5 will be set V < ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS will return to V ...
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Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V individual block lock-bits can be set using the Set Block Lock-Bit command. ...
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STS Configuration Command The Status (STS) pin can be configured to different states using the STS Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued, the device ...
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WSMS BESS ECBLBS 7 6 SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 20H, Block Address Write D0H, Block Address Read Status Register No 0 Suspend SR.7= Block Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= ...
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Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register No Suspend 0 SR.7= Word/Byte Write 1 Full Status Check if Desired Word/byte Write Complete FULL STATUS ...
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Start Write E8H, Start Address Read Extend Status Register 0 Write Buffer XSR.7= Time Out 1 Write Word or Byte Count (N)-1, Start Address Write Buffer Data, Start Address X=1 Yes Abort Buffer Yes Write ...
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FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Read Status Register 1 V Range Error SR. SR.1= Device Protect Error 0 1 Command Sequence SR.4,5= Error 0 1 Multi Word/Byte Write SR.4= Error 0 Multi ...
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Start Write B0H Read Status Register 0 SR. SR.6= 1 (Multi) Word/Byte Write Read Read or Write ? Read Array Data (Multi) Word/Byte Write Loop No Done? Yes Write D0H Block Erase Resumed Figure 10. Block Erase ...
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Start Write B0H Read Status Register 0 SR. (Multi) Word/Byte Write SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH (Multi) Word/Byte Write Read Array Data Resumed Figure 11. (Multi) ...
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Start Write 60H, Block Address Write 01H, Block Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Block Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error PP ...
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Start Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error Device Protect ...
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... V GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5 Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V The V PP block erase, full chip erase, (multi) word/byte write ...
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... When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility or CE# transitions increases usable battery life because data is retained when system power is removed. ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration .....-40°C to +85°C Temperature under Bias............... -40°C to +85°C Storage Temperature........................ -65°C to +125°C Voltage On Any Pin (except ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times ...
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DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Write Current CCW ...
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Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout Voltage during PPLK PP Normal Operations V ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV ...
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Standby V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/ RP#( NOTE: CE# is defined ...
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Standby V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) (DQ ...
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AC CHARACTERISTICS - WRITE OPERATIONS Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# V ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# V Setup to WE# Going High SHWH ...
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V ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#(F) V High Z STS( WP#( RP#( PPH3,2 (V) PP PPLK V NOTES: 1. ...
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ALTERNATIVE CE#-CONTROLLED WRITES Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP# V Setup to ...
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Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP# V Setup to CE# Going High SHEH ...
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V ADDRESSES( CE#( OE#( WE#( DATA(D/ BYTE#(F) V High Z STS( WP#( RP#( PPH3,2 PPLK V NOTES ...
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RESET OPERATIONS High Z STS( RP#( High Z STS( RP#( 2.7/3. RP#( Symbol Parameter t RP# Pulse Low ...
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BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter Word/Byte Write Time t WHQV1 (using W/B write, in word t EHQV1 mode) Word/Byte Write Time t WHQV1 (using W/B write, in byte ...
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Sym. Parameter t Word/Byte Write Time WHQV1 t (using W/B write, in word mode) EHQV1 t Word/Byte Write Time WHQV1 t (using W/B write, in byte mode) EHQV1 Word/Byte Write Time (using multi word/byte write) Block Write Time (using ...
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... ADDITIONAL INFORMATION 7.1 Ordering Information Product line designator for all SHARP Flash products Device Density 160 = 16-Mbit Architecture S = Regular Block Power Supply Type 3 = Smart 3 Technology Operating Temperature Blank = 0°C ~ +70° -40°C ~ +85°C Option Order Code 1 LH28F160S3HNS-L10 LHF16KAS - Access Speed (ns) 10:100ns (3 ...
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A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not ...
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A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp EUROPE SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SINGAPORE SHARP Electronics (Singapore) PTE., Ltd. ...