TB28F800B5B90 Intel, TB28F800B5B90 Datasheet - Page 14

• Manufacturer Part Number: TB28F800B5B90
• Manufacturer: Intel

Specifications of TB28F800B5B90

• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

28F200B5, 28F004/400B5, 28F800B5
3.1.2
With OE# at a logic-high level (V
outputs are disabled. Output pins (if available on
the device) DQ
impedance state.
3.1.3
Deselecting the device by bringing CE# to a logic-
high level (V
which
consumption. In standby, outputs DQ
placed in a high-impedance state independent of
OE#. If deselected during program or erase
operation, the device continues functioning and
consuming
completes.
3.1.4
The 16-bit devices can be configured for either an
8-bit or 16-bit bus width by setting the BYTE# pin
before power-up. This is not applicable to the 8-bit
only E28F004B5.
When BYTE# is set to logic low, the byte-wide
mode is enabled, where data is read and
programmed on DQ
the lowest order address that decodes between the
upper and lower byte. DQ
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode
is enabled, and data is read and programmed on
DQ
3.1.5
RP# at V
also referred to as reset mode.
From read mode, RP# going low for time t
deselects the memory, places output drivers in a
high-impedance state, and turns off all internal
circuits. After return from power-down, a time t
is required until the initial memory access outputs
are valid. A delay (t
return from power-down before a write can be
initiated.
14
0
–DQ
substantially
15
IL
.
After
OUTPUT DISABLE
STANDBY
WORD/BYTE CONFIGURATION
DEEP POWER-DOWN/RESET
IH
initiates the deep power-down mode,
active
) places the device in standby mode
0
this
–DQ
0
PHWL
–DQ
power
15
wake-up
reduces
7
or t
are placed in a high-
and DQ
8
PHEL
until
–DQ
) is required after
interval,
14
15
device
IH
the
/A
), the device
are tri-stated
–1
0
–DQ
operation
becomes
normal
15
power
PHQV
PLPH
are
operation is restored. The CUI resets to read array
mode, and the status register is set to 80H. This
case is shown in Figure 14A.
If RP# is taken low for time t
or erase operation, the operation will be aborted
and the memory contents at the aborted location
(for a program) or block (for an erase) are no longer
valid, since the data may be partially erased or
written. The abort process goes through the
following sequence: When RP# goes low, the
device shuts down the operation in progress, a
process which takes time t
this time t
array mode (if RP# has gone high during t
Figure 14B) or enter deep power-down mode (if
RP# is still logic low after t
both cases, after returning from an aborted
operation, the relevant time t
must be waited before a read or write operation is
initiated, as discussed in the previous paragraph.
However, in this case, these delays are referenced
to the end of t
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, processor expects to read from
the flash memory. Automated flash memories
provide status information when read during
program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
3.1.6
The CUI does not occupy an addressable memory
location. Instead, commands are written into the
CUI using standard microprocessor write timings
when WE# and CE# are low, OE# = V
proper address and data (command) are presented.
The address and data for a command are latched
on the rising edge of WE# or CE#, whichever goes
high first. Figure 16 illustrates a write operation.
PLRH
WRITE
PLRH
, the part will either reset to read
rather than when RP# goes high.
PRELIMINARY
®
PLRH
PLPH
Flash memories allow
PLRH
PHQV
to complete. After
during a program
, Figure 14C). In
or t
IH
PHWL
, and the
/t
PLRH
PHEL
,