TB28F008S5-100 Intel, TB28F008S5-100 Datasheet - Page 5

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TB28F008S5-100

Manufacturer Part Number
TB28F008S5-100
Description
Manufacturer
Intel
Datasheet

Specifications of TB28F008S5-100

Cell Type
NOR
Density
8Mb
Access Time (max)
100ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
20b
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Package Type
SOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8b
Number Of Words
1M
Mounting
Surface Mount
Pin Count
44
Lead Free Status / Rohs Status
Not Compliant
1.0
This datasheet contains 4-, 8-, and 16-Mbit 5 Volt
FlashFile
provides a flash memory overview. Sections 2.0,
through 5.0 describe the memory organization and
functionality.
specifications
temperature product offerings. Section 7.0 contains
ordering information. Finally, the 5 Volt FlashFile
memory
application notes and design tools which are
referenced in Section 8.0.
1.1
The 5 Volt FlashFile memory family maintains
backwards-compatibility with Intel’s 28F008SA. Key
enhancements include:
They share a compatible status register, software
commands, and pinouts. These similarities enable
a clean upgrade from the 28F008SA to 5 Volt
FlashFile products. When upgrading, it is important
to note the following differences:
For more details see application note AP-625,
28F008SC Compatibility with 28F008SA (order
number 292180) .
PRELIMINARY
SmartVoltage Technology
Enhanced Suspend Capabilities
In-System Block Locking
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
V
support low V
program, and lock-bit configuration operations.
Designs that switch V
operations should transition V
To take advantage of SmartVoltage tech-
nology, allow V
PPLK
INTRODUCTION
New Features
has been lowered from 6.5 V to 1.5 V to
family
memory
Section
for
PP
PP
documentation
commercial
connection to 5 V.
specifications.
voltages during block erase,
6.0
PP
covers
PP
off during read
and
to GND.
also
Section
extended
electrical
includes
1.0
1.2
The 5 Volt FlashFile memory family provides
density upgrades with pinout compatibility for the 4-
, 8-, and 16-Mbit densities. The 28F004S5,
28F008S5, and 28F016S5 are high-performance
memories arranged as 512 Kbyte, 1 Mbyte, and
2 Mbyte of 8 bits. This data is grouped in eight,
sixteen, and thirty-two 64-Kbyte blocks which are
individually erasable, lockable, and unlockable in-
system.
organization.
SmartVoltage technology enables fast factory
programming and low power designs. Specifically
designed for 5 V systems, 5 Volt FlashFile
components support read operations at 5 V V
and block erase and program operations at 5 V and
12 V V
program performance which will increase your
factory throughput. With the 5 V V
and V
design. In addition to the voltage flexibility, the
dedicated V
when V
Internal
configures the device for optimized block erase and
program operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within one second (12 V
V
be independently erased 100,000 times (1.6 million
block erases per device). A block erase suspend
operation allows system software to suspend block
erase to read data from or program data to any
other block.
Data is programmed in byte increments typically
within 6
operation permits system software to read data or
execute code from any other flash memory array
location.
PP
), independent of other blocks. Each block can
PP
PP
PP
. The 12 V V
Product Overview
can be tied together for a simple 5 V
V
Figure
PP
s (12 V V
V
PP
28F004S5, 28F008S5, 28F016S5
PPLK
pin gives complete data protection
detection
.
4
PP
PP
illustrates
option renders the fastest
). A program suspend
circuitry
PP
the
automatically
option, V
memory
CC
CC
5

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