CY7C008V-20AC Cypress Semiconductor Corp, CY7C008V-20AC Datasheet
CY7C008V-20AC
Manufacturer Part Number
CY7C008V-20AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheets
1.CY7C008V-20AC.pdf
(18 pages)
2.CY7C008V-20AC.pdf
(18 pages)
3.CY7C008V-20AC.pdf
(18 pages)
4.CY7C008V-20AC.pdf
(18 pages)
Specifications of CY7C008V-20AC
Density
512Kb
Access Time (max)
20ns
Operating Supply Voltage (typ)
5V
Package Type
TQFP
Operating Temp Range
0C to 70C
Supply Current
265mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
8b
Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-06044 Rev. *B
Features
Notes:
1.
2.
3.
• True Dual-Ported memory cells which allow simulta-
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
Logic Block Diagram
A
A
CE
OE
R/W
SEM
BUSY
INT
R/W
CE
CE
OE
I/O
neous access of the same memory location
— Active: I
— Standby: I
0L
0L
I/O
A
BUSY is an output in master mode and an input in slave mode.
L
0
L
0L
0L
1L
L
–A
–A
L
–A
0
L
L
L
–I/O
–I/O
15
[2]
[2]
L
15/16L
15/16L
[3]
for 64K devices; A
7
7/8L
for x8 devices; I/O
[1]
CC
SB3
= 115 mA (typical)
CE
= 10 A (typical)
16/17
L
For the most recent information, visit the Cypress web site at www.cypress.com
8/9
0
–A
0
–I/O
16
for 128K.
8
for x9 devices.
Address
Decode
16/17
•
3901 North First Street
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Mas-
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flag for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 100-pin TQFP
ter/Slave chip select when using more than one device
between ports
Control
I/O
•
San Jose
Dual-Port Static RAM
3.3V 64K/128K x 8/9
Address
Decode
16/17
•
CA 95134
CY7C008V/009V
CY7C018V/019V
Revised December 27, 2002
16/17
8/9
CE
R
•
I/O
A
A
408-943-2600
[3]
0R
0R
0R
–A
–A
–I/O
[2]
[2]
BUSY
SEM
R/W
15/16R
15/16R
CE
CE
R/W
[1]
INT
OE
OE
CE
7/8R
0R
1R
R
R
R
R
R
R
R
R
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