CY7C009-12AC Cypress Semiconductor Corp, CY7C009-12AC Datasheet

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CY7C009-12AC

Manufacturer Part Number
CY7C009-12AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C009-12AC

Density
1Mb
Access Time (max)
12ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
325mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
8b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C009-12AC
Manufacturer:
CY
Quantity:
15
Cypress Semiconductor Corporation
Document #: 38-06041 Rev. *E
Features
Notes:
CY7C008/009
CY7C018/01964K/128K x 8/9 Dual-Port Static RAM
1. See page 6 for Load Conditions.
2. I/O
3. A
4. BUSY is an output in master mode and an input in slave mode.
• True Dual-Ported memory cells that allow simultaneous
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12
• Low operating power
• Fully asynchronous operation
Logic Block Diagram
access of the same memory location
— Active: I
— Standby: I
A
A
CE
OE
R/W
SEM
BUSY
INT
R/W
CE
CE
OE
I/O
0
–A
0L
0L
0
–I/O
L
0L
L
0L
1L
–A
–A
15
L
L
L
L
L
–I/O
for 64K devices; A
7
[3]
[3]
L
15/16L
15/16L
for x8 devices; I/O
[4]
7/8L
[2]
CC
SB3
= 180 mA (typical)
= 0.05 mA (typical)
CE
0
16/17
–A
L
0
8/9
–I/O
16
[1]
for 128K.
8
/15/20 ns
for x9 devices.
Address
Decode
16/17
198 Champion Court
Control
I/O
64K/128K x 8/9 Dual-Port Static RAM
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flags for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP; Pb-Free packages available
Master/Slave chip select when using more than one
device
between ports
Control
I/O
San Jose
,
Address
Decode
CA 95134-1709
16/17
Revised March 19, 2010
16/17
8/9
CE
CY7C008/009
CY7C018/019
R
I/O
A
A
408-943-2600
[4]
0R
0R
0R
–A
–A
–I/O
[3]
[3]
BUSY
SEM
R/W
15/16R
15/16R
R/W
CE
CE
[2]
INT
OE
OE
CE
7/8R
0R
1R
R
R
R
R
R
R
R
R
[+] Feedback

Related parts for CY7C009-12AC

CY7C009-12AC Summary of contents

Page 1

... CY7C018/01964K/128K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells that allow simultaneous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • 0.35-micron CMOS for optimum speed/power [1] • ...

Page 2

... Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C008/009 and CY7C018/019 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View CY7C009 (128K x 8) CY7C008 (64K CY7C008/009 CY7C018/019 ...

Page 3

Pin Configurations (continued) 100 A7L 3 A8L 4 A9L 5 A10L 6 A11L 7 A12L 8 A13L 9 A14L 10 A15L 11 [6] A16L 12 VCC ...

Page 4

... DC Input Voltage ......................................... –0.5V to +7.0V Notes: 7. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 8. Pulse width < 20 ns. 9. Industrial parts are available in CY7C009 and CY7C019 only. Document #: 38-06041 Rev. *E Description Chip Enable (CE is LOW when CE Read/Write Enable ...

Page 5

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage OH (V =Min –4.0 mA Output LOW Voltage OL (V =Min +4.0 mA Input HIGH Voltage IH V ...

Page 6

AC Test Loads and Waveforms 893Ω OUTPUT 347Ω (a) Normal Load (Load 1) 3.0V GND AC Test Loads (Applicable to -12 only 50Ω 50Ω 0 OUTPUT C ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address Change OHA [14 LOW to Data Valid ACE t OE LOW to ...

Page 8

Switching Characteristics Over the Operating Range Parameter Description [19] BUSY TIMING t BUSY LOW from Address Match BLA t BUSY HIGH from Address Mismatch BHA t BUSY LOW from CE LOW BLC t BUSY HIGH from CE HIGH BHC t ...

Page 9

Switching Waveforms Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (Either Port CE/OE Access DATA OUT CURRENT I SB [22, 24, ...

Page 10

Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [31 R/W NOTE 33 DATA OUT DATA IN Write Cycle No Controlled Timing ADDRESS [28 R/W DATA IN Notes: 27. ...

Page 11

Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Timing Diagram of Semaphore Contention A – R/W L SEM L A –A ...

Page 12

Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 39 LOW. ...

Page 13

Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Busy Timing Diagram No. 2 (Address ...

Page 14

... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE FFFF (1FFFF for CY7C009/19 R/W L INT R [42] t INS Right Side Clears INT : R ADDRESS R INT R Right Side Sets INT : L ADDRESS WRITE FFFE (1FFFE for CY7C009/19 R/W R INT L [42] t INS Left Side Clears INT ...

Page 15

... CY7C008/18, 1FFFF for the CY7C009/19) is the mailbox for the right port and the second-highest memory location (FFFE for the CY7C008/18, 1FFFE for the CY7C009/19) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox ...

Page 16

... Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Notes: 43. A and A , 1FFFF/1FFFE for the CY7C009/019. 0L–16L 0R–16R 44. If BUSY = L, then no change. R 45. If BUSY = L, then no change. ...

Page 17

... Ordering Information 128K x 8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C009-15AXC Package Diagram Figure 1. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06041 Rev. *E Package Name ...

Page 18

... Change pin 85 from BUSYL to BUSYR (pg. 3) Power up requirements added to Maximum Ratings Information Removed cross information from features section Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C008-15AXC, CY7C009-15AXC Removed inactive parts from ordering information table Updated package diagram CY7C008/009 CY7C018/019 Page ...

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