CY7C0241-25AC Cypress Semiconductor Corp, CY7C0241-25AC Datasheet
CY7C0241-25AC
Specifications of CY7C0241-25AC
Related parts for CY7C0241-25AC
CY7C0241-25AC Summary of contents
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... Features ■ True dual-ported memory cells, which allow simultaneous reads of the same memory location [1] ■ organization (CY7C024/024A ■ organization (CY7C0241) ■ organization (CY7C025) ■ organization (CY7C0251) ■ 0.65 micron CMOS for optimum speed and power ■ High speed access ■ Low operating power: I ...
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... Notes 2. BUSY is an output in master mode and an input in slave mode. 3. I/O –I/O on the CY7C0241/0251 I/O –I/O on the CY7C0241/0251 the CY7C025/0251. 12L the CY7C025/0251. 12R Document #: 38-06035 Rev. *D I/O I/O CONTROL CONTROL MEMORY ADDRESS ADDRESS ARRAY DECODER DECODER INTERRUPT CE CE ...
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Pin Configurations (continued) 100 I/O 10L 5 I/O 6 11L I/O 12L 7 I/O 13L 8 GND 9 I/O 10 14L I/O 11 15L GND ...
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Selection Guide Parameter Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for I (mA) SB1 Architecture The CY7C024/024A/0241 and CY7C025/0251 consist of an array of 4K words of 16/18 bits each and 8K words of 16/18 bits ...
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Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner ...
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Table 3. Semaphore Operation Example I/O 0 Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore ...
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Maximum Ratings [10] Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage to Ground Potential................–0.3V to ...
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Electrical Characteristics Over the Operating Range (continued) Parameter Description I Operating Current V CC Outputs Disabled I Standby Current CE SB1 (Both Ports TTL Levels Standby Current CE SB2 (One Port TTL Level ...
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Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Output Hold From Address OHA Change [15 LOW to Data Valid ACE t OE LOW to ...
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Switching Characteristics Over the Operating Range (continued) Parameter Description [20] Busy Timing t BUSY LOW from Address BLA Match t BUSY HIGH from Address BHA Mismatch t BUSY LOW from CE LOW BLC t BUSY HIGH from CE HIGH BHC ...
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Switching Waveforms Figure 4. Read Cycle No. 1 (Either Port Address Access) ADDRESS OHA DATA OUT PREVIOUS DATA VALID Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) CE and DATA OUT ...
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Switching Waveforms (continued) Figure 7. Write Cycle No. 1: R/W Controlled Timing ADDRESS OE [32,33 R/W NOTE 35 DATA OUT DATA IN Figure 8. Write Cycle No Controlled Timing ADDRESS [32,33 R/W ...
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Switching Waveforms (continued) Figure 9. Semaphore Read After Write Timing, Either Side A –A VALID ADRESS SEM I R/W OE Figure 10. Timing Diagram of Semaphore Contention A – R/W L ...
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Switching Waveforms (continued) Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 41. CE ...
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Switching Waveforms (continued) Figure 13. Busy Timing Diagram No.1 (CE Arbitration) CE Valid First: L ADDRESS L BUSY R CE Valid First: R ADDRESS L BUSY L Figure 14. Busy Timing Diagram ...
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Switching Waveforms (continued) Left Side Sets INT : R ADDRESS WRITE FFF (1FFF CY7C025 R/W L INT R [44] t INS Right Side Clears INT : R ADDRESS R INT R ...
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... CY7C024-35JXC CY7C024–35AI CY7C024-35AXI CY7C024–35JI CY7C024-35JXI 55 CY7C024–55AC CY7C024-55AXC CY7C024–55JC CY7C024-55JXC CY7C024–55AI CY7C024-55AXI CY7C024–55JI CY7C024-55JXI Ordering Information ( Dual-Port SRAM) Speed (ns) Ordering Code 15 CY7C025–15AC CY7C025-15AXC CY7C025–15JC CY7C025-15JXC CY7C025–15AI CY7C025-15AXI Document #: 38-06035 Rev. *D Package Name Package Type ...
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... Ordering Code 15 CY7C0241–15AC CY7C0241-15AXC CY7C0241–15AI CY7C0241-15AXI 25 CY7C0241–25AC CY7C0241-25AXC CY7C0241–25AI CY7C0241-25AXI 35 CY7C0241–35AC CY7C0241-35AXC CY7C0241–35AI CY7C0241-35AXI Document #: 38-06035 Rev. *D (continued) Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb Free Thin Quad Flat Pack ...
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... Ordering Information ( Dual-Port SRAM) Speed (ns) Ordering Code 55 CY7C0241–55AC CY7C0241-55AXC CY7C0241–55AI CY7C0241-55AXI Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C0251–15AC CY7C0251–15AXC 25 CY7C0251–25AC CY7C0251-25AXC CY7C0251–25AI CY7C0251–25AXI 35 CY7C0251–35AC CY7C0251–35AXC CY7C0251–35AI CY7C0251–35AXI 55 CY7C0251–55AC CY7C0251–55AXC CY7C0251– ...
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Package Diagrams Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Figure 17. 84-Pin Pb Free Plastic Leaded Chip Carrier J83 Document #: 38-06035 Rev. *D CY7C024/024A/0241 CY7C025/0251 51-85048-*C 51-85006-*A Page [+] Feedback ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...