CY7C024-25AI Cypress Semiconductor Corp, CY7C024-25AI Datasheet - Page 12

• Manufacturer Part Number: CY7C024-25AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C024-25AI

• Density: 64Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 12b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 290mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 16b
• Number Of Words: 4K
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Notes
Document #: 38-06035 Rev. *D
28. R/W must be HIGH during all address transitions.
29. A write occurs during the overlap (t
30. t
31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
32. To access RAM, CE = V
33. To access upper byte, CE = V
34. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
placed on the bus for the required t
the specified t
To access lower byte, CE = V
HA
DATA IN
DATA IN
[32,33]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
[32,33]
R/W
R/W
OE
PWE
.
IL
, SEM = V
IL
, LB = V
IL
, UB = V
t
t
SA
SA
IH
NOTE 35
SD
SCE
Figure 7. Write Cycle No. 1: R/W Controlled Timing
IL
Figure 8. Write Cycle No. 2: CE Controlled Timing
.
(continued)
, SEM = V
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
IL
or t
, SEM = V
PWE
) of a LOW CE or SEM and a LOW UB or LB.
IH
.
IH
.
t
HZWE
[34]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[31]
t
t
SD
SD
PWE
or (t
HZWE
t
t
HA
HA
[28, 29, 30, 36]
+ t
[28, 29, 30, 31]
SD
t
t
HD
HD
) to allow the I/O drivers to turn off and data to be
t
LZWE
CY7C024/024A/0241
t
HZOE
CY7C025/0251
NOTE 35
[34]
Page 12 of 21
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