CY7C09579V-67AC Cypress Semiconductor Corp, CY7C09579V-67AC Datasheet - Page 14

• Manufacturer Part Number: CY7C09579V-67AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09579V-67AC

• Density: 1.125Mb
• Access Time (max): 8ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 15b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 340mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 32K
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Pipelined Read-to-Write-to-Read (OE = V
Notes
Document Number: 38-06054 Rev. *D
27. Addresses do not have to be accessed sequentially since ADS = V
28. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
29. CE = ADS = CNTEN = V
30. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
ADDRESS
DATA
DATA
CLK
R/W
OUT
CE
IN
t
t
t
SW
SC
SA
A
IL
t
n
; CNTRST = V
CH2
t
CYC2
t
t
t
HW
HC
HA
(continued)
t
CL2
IH
.
A
READ
n+1
t
CD2
IL
t
SW
)
[27, 28, 29, 30]
Q
n
IL
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
A
n+2
t
CKHZ
NO OPERATION
t
HW
t
SD
A
D
n+2
n+2
t
HD
WRITE
A
n+3
t
CKLZ
READ
CY7C09569V
CY7C09579V
A
n+4
t
CD2
Page 14 of 32
Q
n+3
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