CY7C1360A-200AI Cypress Semiconductor Corp, CY7C1360A-200AI Datasheet - Page 9

• Manufacturer Part Number: CY7C1360A-200AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1360A-200AI

• Density: 9Mb
• Access Time (max): 3ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 510mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05258 Rev. *A
Burst Address Table (MODE = NC/V
Notes:
Truth Table
A
00
01
10
11
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “sleep”
Address (ex-
3.
4.
5.
6.
7.
8.
9.
[1:0]]
ternal)
X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For X36 product, Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, Write = L means [BWE + BWa*BWb]*GW equals LOW. Write = H means [BWE + BWa*BWb]*GW equals HIGH.
BWa enables Write to DQa. BWb enables Write to DQb. BWc enables Write to DQc. BWd enables Write to DQd.
All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
Suspending burst generates wait cycle.l
For a Write operation following a Read operation, OE must be HIGH before the input-data-required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
First
Next Cycle
[3, 4, 5, 6, 7, 8, 9]
A
01
00
11
10
[1:0]
(internal)
Address
Second
A
10
11
00
01
[1:0]
(internal)
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
None
Address
Address Used ZZ
Third
A
11
10
01
00
CC
[1:0]
(internal)
Address
)
Fourth
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
1
CE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
3
CE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Burst Address Table (MODE = GND)
0
0
1
1
1
A
00
01
10
11
2
[1:0]]
(external)
Address
CE
First
X
X
X
X
X
X
X
X
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
ADSP ADSC ADV
X
X
X
X
X
X
X
X
X
0
0
1
1
0
1
1
1
1
1
1
1
1
1
A
01
10
11
00
[1:0]
(internal)
Address
Second
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
0
0
1
1
A
10
11
00
01
[1:0]
(internal)
Address
Third
OE
X
X
X
X
X
X
X
1
1
1
1
X
X
X
X
X
X
X
X
0
0
0
0
CY7C1360A
CY7C1362A
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
A
11
00
01
10
Page 9 of 28
[1:0]
(internal)
Address
Fourth
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
DQ