CY7C1360B-200AC Cypress Semiconductor Corp, CY7C1360B-200AC Datasheet - Page 8

• Manufacturer Part Number: CY7C1360B-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1360B-200AC

• Density: 9Mb
• Access Time (max): 3ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 220mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05291 Rev. *C
CY7C1360B–Pin Definitions
V
V
MODE
TDO
TDI
TMS
TCK
NC
SSQ
DDQ
Name
5,10,21,26,
4,11,20,27,
55,60,71,
54,61,70,
14,16,66,
42,39,38
Enable
3-Chip
TQFP
76
77
31
-
-
-
-
5,10,21,26,
4,11,20,27,
55,60,71,
54,61,70,
14,16,38,
39,42,43,
Enable
2-Chip
TQFP
66,
76
77
31
-
-
-
-
(continued)
R1,T1,T2,
A1,F1,J1,
A7,F7,J7,
L4,5J,5R,
M1,U1,
B1,C1,
B7,C7,
M7,U7
J3,D4,
6T,6U,
BGA
R3
U5
U3
U2
U4
R7
-
D9,E3,E9,F
C10,H1,H3,
A11,B1,C2,
N10,P1,A1,
B11,P2,R2,
C3,C9,D3,
L9,M3,M9,
N2,N5,N7,
K3,K9,L3,
G9,J3,J9,
3,F9,G3,
H9,H10,
N3,N9
fBGA
R1
R5
R7
N6
P7
P5
-
Synchronous
Synchronous
Synchronous
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
JTAG serial
JTAG serial
JTAG serial
I/O Ground
I/O Power
Supply
output
Input-
Static
input
input
I/O
-
Ground for the I/O circuitry.
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode pin has an internal pull-up.
Serial data-out to the JTAG circuit. Delivers data
on the negative edge of TCK. If the JTAG feature is
not being utilized, this pin should be disconnected.
This pin is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected
to V
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected
to V
feature is not being utilized, this pin must be
connected to V
packages.
No Connects. Not internally connected to the die
DD
DD
. This pin is not available on TQFP packages.
. This pin is not available on TQFP packages.
SS
. This pin is not available on TQFP
Description
CY7C1360B
CY7C1362B
Page 8 of 34
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