AD7755AARS Analog Devices Inc, AD7755AARS Datasheet - Page 12

• Manufacturer Part Number: AD7755AARS
• Manufacturer: Analog Devices Inc

Specifications of AD7755AARS

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 24
• Mounting: Surface Mount
• Package Type: SSOP
• Case Height: 1.78(Max)mm
• Screening Level: Industrial
• Lead Free Status / Rohs Status: Not Compliant

AD7755
Figure 25 shows two typical connections for Channel V2. The
first option uses a PT (potential transformer) to provide com-
plete isolation from the mains voltage. In the second option the
AD7755 is biased around the neutral wire, and a resistor divider
is used to provide a voltage signal that is proportional to the line
voltage. Adjusting the ratio of Ra, Rb and VR is also a conve-
nient way of carrying out a gain calibration on the meter.
POWER SUPPLY MONITOR
The AD7755 contains an on-chip power supply monitor. The
Analog Supply (AV
If the supply is less than 4 V
This is useful to ensure correct device start-up at power-up and
power-down. The power supply monitor has built in hysteresis
and filtering. This gives a high degree of immunity to false trig-
gering due to noisy supplies.
As can be seen from Figure 26, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is about 5%. The
power supply and decoupling for the part should be such that
the ripple at AV
normal operation.
PHASE
PHASE
INTERNAL
RESET
NEUTRAL
NEUTRAL
AV
5V
4V
0V
DD
RESET
DD
Ra
VR
Rb
DD
does not exceed 5 V
CT
) is continuously monitored by the AD7755.
Ra >> Rb + VR
Rb + VR = Rf
Cf
AGND
660mV
ACTIVE
TIME
660mV
5%, the AD7755 will be reset.
Rf
Rf
Rf
5% as specified for
RESET
Cf
Cf
Cf
V2P
V2N
V2P
V2N
HPF and Offset Effects
Figure 27 shows the effect of offsets on the real power calcula-
tion. As can be seen, an offset on Channel 1 and Channel 2 will
contribute a dc component after multiplication. Since this dc
component is extracted by the LPF and used to generate the
real power information, the offsets will have contributed a con-
stant error to the real power calculation. This problem is easily
avoided by enabling the HPF (i.e., pin AC/DC is set logic high)
in Channel 1. By removing the offset from at least one channel,
no error component can be generated at dc by the multiplica-
tion. Error terms at cos( t) are removed by the LPF and the
digital-to-frequency conversion—see Digital-to-Frequency
Conversion section.
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 28 and 29 show the phase error between
channels with the compensation network activated. The AD7755
is phase compensated up to 1 kHz as shown. This will ensure
correct active harmonic power calculation even at low power
factors.
V
V
V
2
cos
2
I
I
V
OS
V
t
OS
cos
V
I
OS
2
V
I
0
OS
2
I
OS
t
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
V
I
OS
cos
I
V
OS
FREQUENCY – RAD/S
OS
I
t
cos
V
I
I
OS
t
2
I
OS
V
cos
t