CY7C1324F-117AC Cypress Semiconductor Corp, CY7C1324F-117AC Datasheet
CY7C1324F-117AC
Specifications of CY7C1324F-117AC
Related parts for CY7C1324F-117AC
CY7C1324F-117AC Summary of contents
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... Offered in JEDEC-standard 100-pin TQFP package • “ZZ” Sleep Mode option Functional Description [1] The CY7C1324F is a 131,072 x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is Logic Block Diagram ADDRESS ...
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... Maximum Access Time Maximum Operating Current Maximum Standby Current Pin Configurations DDQ DDQ BYTE DDQ DQP DDQ Document #: 38-05431 Rev. ** 133 MHz 117 MHz 6.5 7.5 225 220 40 40 100-Pin TQFP CY7C1324F CY7C1324F Unit DDQ DQP DDQ BYTE DDQ DDQ Page [+] Feedback ...
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... Read cycle. The direction of the pins is controlled When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP are placed in a three-state condition. [A:B] Power supply inputs to the core of the device. Ground for the device. CY7C1324F , CE , and ...
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... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). CDV The CY7C1324F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... CE ZZ ADSP ADSC and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals ( CY7C1324F Third Fourth Address Address , Min. Max. Unit CYC 2t ns CYC 2t ns CYC 0 ns ADV WE OE CLK L-H Three-State L-H Three-State L-H Three-State L-H Three-State L-H Three-State ...
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... Truth Table for Read/Write [2, 3] Function Read Read Write Byte (A, DQP ) A Write Byte (B, DQP ) B Write All Bytes Write All Bytes Document #: 38-05431 Rev ADSP ADSC BWE CY7C1324F ADV WE OE CLK L L-H Three-State L L-H Three-State L L-H Three-State L-H Three-State L L-H Three-State L L Page [+] Feedback ...
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... CYC IL (min.) within 200 ms. During this time V < V and CY7C1324F Ambient ] Temperature DDQ 0°C to +70°C 3.3V 3.3V –5% −5%/+10 –40°C to +85°C CY7C1324F Min. Max. Unit 3.135 3.6 V 3.135 3.6 V 2.4 V 0 –0.3 0.8 V −5 µ ...
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... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1324F TQFP Package Unit °C/W 41.83 °C/W 9.99 Max. Unit ...
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... CEH Document #: 38-05431 Rev. ** [9, 10] 133 MHz 117 MHz Min. Max. Min. 1.5 2.0 1.5 2.0 1.5 2.0 1.5 2.0 1.5 2.0 1.5 2.0 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 CY7C1324F Max. Unit Page [+] Feedback ...
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... ADVS ADVH ADV suspends burst. t CDV t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1324F Deselect Cycle t CHZ Q( Q(A2 Burst wraps around to its initial state is HIGH LOW HIGH Page [+] Feedback ...
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... Full width Write can be initiated by either GW LOW HIGH, BWE LOW and BW Document #: 38-05431 Rev WEH WES ADV suspends burst. D(A2 BURST WRITE DON’T CARE UNDEFINED LOW [A:B] CY7C1324F ADSC extends burst. t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page [+] Feedback ...
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... The data bus (Q) remains in High-Z following a Write cycle unless an ADSP , ADSC , or ADV cycle is performed. 18 HIGH. Document #: 38-05431 Rev WES WEH OELZ D(A3) t CDV Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1324F A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... Ordering Information Speed (MHz) Ordering Code 133 CY7C1324F-133AC 117 CY7C1324F-117AC CY7C1324F-117AI Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 20. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05431 Rev. ** High-Z DON’ ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. DIMENSIONS ARE IN MILLIMETERS 0.30±0.08 0.65 12°±1° TYP. (8X STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. CY7C1324F 1.40±0.05 A SEE DETAIL 0.20 MAX. 1.60 MAX. 51-85050-*A Page [+] Feedback ...
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... Document History Page Document Title: CY7C1324F 2-Mb (128K x 18) Flow-Through Sync SRAM Document Number: 38-05431 REV. ECN NO. Issue Date ** 200780 See ECN Document #: 38-05431 Rev. ** Orig. of Change Description of Change NJY New Data Sheet CY7C1324F Page [+] Feedback ...