CY7C1347B-166BGC Cypress Semiconductor Corp, CY7C1347B-166BGC Datasheet - Page 5

• Manufacturer Part Number: CY7C1347B-166BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347B-166BGC

• Density: 4Mb
• Access Time (max): 3.5ns
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Supply Current: 420mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(166-MHz device).
The CY7C1347B supports secondary cache in systems utiliz-
ing either a linear or interleaved burst sequence. The inter-
leaved burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs (A
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the Output Register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
to A
advancement logic while being delivered to the RAM core. The
1
1
[16:0]
, CE
, CE
2
2
is loaded into the Address Register and the address
, CE
, CE
3
3
are all asserted active, and (3) the write signals
are all asserted active. The address presented
[3:0]
) inputs. A Global Write
1
, CE
2
, CE
CO
) is 3.5 ns
3
) and an
[16:0]
1
1
)
5
write signals (GW, BWE, and BW
nored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
the corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW
ity that is described in the Write Cycle Description table. As-
serting the Byte Write Enable input (BWE) with the selected
Byte Write (BW
sired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347B is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
output drivers. As a safety precaution, DQ
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A
vancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347B is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
output drivers. As a safety precaution, DQ
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1347B provides a two-bit wraparound counter, fed
by A
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
ear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
[16:0]
[3:0]
[1:0]
is loaded into the address register and the address ad-
signals. The CY7C1347B provides byte write capabil-
, that implements either an interleaved or linear burst
[31:0]
[31:0]
and DP
and DP
[3:0]
[3:0]
) are asserted active to conduct a write to
) input will selectively write to only the de-
[3:0]
[3:0]
[31:0]
1
inputs. Doing so will three-state the
inputs. Doing so will three-state the
, CE
and DP
2
, CE
[3:0]
[31:0]
3
) and ADV inputs are ig-
CY7C1347B
[3:0]
are all asserted active,
and DP
[31:0]
[31:0]
inputs is written into
and DP
and DP
[3:0]
is written
[3:0]
[3:0]
are
are