AM29PL160CB-90SI AMD (ADVANCED MICRO DEVICES), AM29PL160CB-90SI Datasheet - Page 23

• Manufacturer Part Number: AM29PL160CB-90SI
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29PL160CB-90SI

• Lead Free Status / Rohs Status: Not Compliant

7.1
7.2
7.3
May 21, 2008 S29GL-A_00_A12
7.2.1
Word/Byte Configuration
Requirements for Reading Array Data
Writing Commands/Command Sequences
Page Mode Read
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic 1, the device is in word configuration, DQ0–DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
To read array data from the outputs, the system must drive the CE# and OE# pins to V
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at V
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. The device remains enabled for
read access until the command register contents are altered.
See
Characteristics on page 72
on page 70
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read
operation. This mode provides faster read access speed for random locations within a page. The page size of
the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2.
Address bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is
an asynchronous operation; the microprocessor supplies the specific word location.
The random or initial page access is equal to t
locations specified by the microprocessor falls within that page) is equivalent to t
deasserted and reasserted for a subsequent access, the access time is t
accesses are obtained by keeping the read-page addresses constant and changing the intra-read page
addresses.
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to V
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The
Program Command Sequence on page 53
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 7.22 on page 45
Refer to
Characteristics on page 72
Reading Array Data on page 52
DC Characteristics on page 70
IH
for the active current specification on reading array data.
.
indicate the address space that each sector occupies.
D a t a
for timing specifications and the timing diagram. Refer to
contains timing specification tables and timing diagrams for write operations.
S h e e t
for more information. Refer to the AC Read-Only Operations table in
for the active current specification for the write mode.
S29GL-A
contains details on programming data to the device using both
ACC
or t
CE
and subsequent page read accesses (as long as the
IL
, and OE# to V
ACC
or t
IH
Table 7.4 on page 27
PACC
CE
.
. Fast page mode
DC Characteristics
. When CE# is
IL
. CE# is the power
AC
Word
to
AC
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