PPC440GX-3NF533C Applied Micro Circuits Corporation, PPC440GX-3NF533C Datasheet - Page 54

• Manufacturer Part Number: PPC440GX-3NF533C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3NF533C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 533MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / Rohs Status: Compliant

440GX – Power PC 440GX Embedded Processor
54
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ to GND)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to 3.3V) or pull-down (recommended value is 1kΩ to GND)
UART0_DTR
UART0_RTS
UART0_RI
UART1_Rx
UART1_Tx
UART1_DSR/CTS
UART1_RTS/DTR
IIC Peripheral Interface
IIC0SClk
IIC0SDA
IIC1SClk
IIC1SDA
Interrupts Interface
IRQ00:10
IRQ11:12
IRQ13:17
JTAG Interface
TCK
TDI
TDO
TMS
TRST
required
Signal Name
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
UART1 Receive data.
UART1 Transmit data.
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
UART1 Request To Send or Data Terminal Ready. The choice is
determined by a DCR register bit setting.
IIC0 Serial Clock.
IIC0 Serial Data.
IIC1 Serial Clock.
IIC1 Serial Data.
External interrupt Requests 0 through 10.
External interrupt Requests 11 through 12.
External interrupt Requests 13 through 17.
Test Clock.
Test Data In.
Test Data Out.
Test Mode Select.
Test Reset. During chip power-up, this signal must be low from the
start of V
stable in order to initialize the JTAG controller.
DD
ramp-up until at least 16 SysClk cycles after V
(Sheet 6 of 8)
Description
DD
is
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Revision 1.20 – June 9, 2009
O
O
O
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V PCI
w/pull-up
w/pull-up
w/pull-up
w/pull-up
3.3V IIC
3.3V IIC
Type
Data Sheet
Notes
1, 4
1, 4
1, 4
1, 4
1, 4
1, 2
1, 2
1, 2
1, 2
1, 5
4
4
1
1
5
4
AMCC