7025L25PF IDT, Integrated Device Technology Inc, 7025L25PF Datasheet

7025L25PF

Manufacturer Part Number
7025L25PF
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 7025L25PF

Density
128Kb
Access Time (max)
25ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
26b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
220mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
16b
Number Of Words
8K
Lead Free Status / Rohs Status
Not Compliant
Features
Functional Block Diagram
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
©2008 Integrated Device Technology, Inc.
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7025S
– IDT7025L
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
Active: 750mW (typ.)
Standby: 5mW (typ.)
Active: 750mW (typ.)
Standby: 1mW (typ.)
I/O
I/O
8L
0L
BUSY
-I/O
-I/O
SEM
R/W
A
INT
UB
CE
OE
LB
A
12L
15L
0L
7L
L
L
L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
13
Control
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
M/S
1
IDT7025 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Control
I/O
13
Decoder
Address
CE
OE
R/W
R
R
R
OCTOBER 2008
2683 drw 01
IDT7025S/L
R/W
LB
CE
OE
I/O
I/O
BUSY
A
A
SEM
UB
INT
12R
0R
R
8R
0R
R
R
R
R
R
R
(2)
-I/O
-I/O
R
(1,2)
15R
7R
DSC 2683/10

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7025L25PF Summary of contents

Page 1

Features True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 20/25/35/55/70ns (max.) – Industrial: 55ns (max.) – Commercial: 15/17/20/25/35/55ns (max.) Low-power operation – IDT7025S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7025L ...

Page 2

IDT7025S/L High-Speed Dual-Port Static RAM Description The IDT7025 is a high-speed Dual-Port Static RAM. The IDT7025 is designed to be used as a stand-alone 128K-bit Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM ...

Page 3

IDT7025S/L High-Speed Dual-Port Static RAM Pin Configurations (1,2, I/O I I/O I/O 10L I/O I/O 11L I/O I/O 13L 12L 72 ...

Page 4

IDT7025S/L High-Speed Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port R/W R 12L ...

Page 5

IDT7025S/L High-Speed Dual-Port Static RAM Truth Table I: Non-Contention Read/Write Control (1) Inputs R ...

Page 6

IDT7025S/L High-Speed Dual-Port Static RAM Absolute Maximum Ratings Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias T Storage -65 to ...

Page 7

IDT7025S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the 0perating Temperature and Supply Voltage Range Symbol Parameter Test Condition Dynamic Operating CC , Outputs Disabled IL Current SEM = V IH (Both ...

Page 8

IDT7025S/L High-Speed Dual-Port Static RAM Data Retention Characteristics Over All Temperature Ranges (L Version Only) Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Dese lect to Data Retention ...

Page 9

IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t (3) Chip Enable Access Time ACE ...

Page 10

IDT7025S/L High-Speed Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends ...

Page 11

IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Symbol Parameter WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW ...

Page 12

IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE ( SEM ( ( R/W (4) DATA OUT DATA IN Timing Waveform of ...

Page 13

IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM DATA R/W OE Write Cycle NOTE ...

Page 14

IDT7025S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter BUSY TIMING (M BUSY Access Time from Address Match t BAA BUSY Disable Time from Address ...

Page 15

IDT7025S/L High-Speed Dual-Port Static RAM Timing Waveform of Write Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier ...

Page 16

IDT7025S/L High-Speed Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S ...

Page 17

IDT7025S/L High-Speed Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same ...

Page 18

... IH the memory location 1FFF user-defined, since addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table I for the interrupt operation ...

Page 19

IDT7025S/L High-Speed Dual-Port Static RAM Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to ...

Page 20

IDT7025S/L High-Speed Dual-Port Static RAM that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the ...

Page 21

IDT7025S/L High-Speed Dual-Port Static RAM variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual- Port RAM or other shared resources into eight parts. Semaphores ...

Page 22

IDT7025S/L High-Speed Dual-Port Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type NOTE: 1. Industrial range is available on selected PLCC packages in standard power. For other speeds, packages and powers contact your ...

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