LMK03033CISQE National Semiconductor, LMK03033CISQE Datasheet - Page 13

• Manufacturer Part Number: LMK03033CISQE
• Manufacturer: National Semiconductor

Specifications of LMK03033CISQE

• Lead Free Status / Rohs Status: Not Compliant

1.8 CLKout OUTPUT STATES
Each clock output may be individually enabled with the
CLKoutX_EN bits. Each individual output enable control bit is
gated with the Global Output Enable input pin (GOE) and the
Global Output Enable bit (EN_CLKout_Global).
All clock outputs can be disabled simultaneously if the GOE
pin is pulled low by an external signal or EN_CLKout_Global
is set to 0.
When an LVDS output is in the Off state, the outputs are at a
voltage of approximately 1.5 volts. When an LVPECL output
is in the Off state, the outputs are at a voltage of approximately
1 volt.
1.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT
The GOE pin provides an internal pull-up resistor as shown
on the functional block diagram. If it is not terminated exter-
nally, the clock output states are determined by the Clock
Output
EN_CLKout_Global bit.
By programming the PLL_MUX register to Digital Lock Detect
Active High, the Lock Detect (LD) pin can be connected to the
GOE pin in which case all outputs are set low automatically if
the synthesizer is not locked.
1.10 POWER ON RESET
When supply voltage to the device increases monotonically
from ground to Vcc, the power on reset circuit sets all registers
to their default values, see the programming section for more
information on default register values. Voltage should be ap-
plied to all Vcc pins simultaneously.
1.11 DIGITAL LOCK DETECT
The PLL digital lock detect circuitry compares the difference
between the phase of the inputs of the phase detector to a
RC generated delay of ε. To indicate a locked state the phase
error must be less than the ε RC delay for 5 consecutive ref-
erence cycles. Once in lock, the RC delay is changed to
approximately δ. To indicate an out of lock state, the phase
error must become greater δ. The values of ε and δ are shown
in the table below:
To utilize the digital lock detect feature, PLL_MUX must be
programmed for "Digital Lock Detect (Active High)" or "Digital
Lock Detect (Active Low)." When one of these modes is pro-
grammed the state of the LD pin will be set high or low as
determined by the description above as shown in
When the device is in power down mode and the LD pin is
programmed for a digital lock detect function, LD will show a
"no lock detected" condition which is low or high given active
high or active low circuitry respectively.
The accuracy of this circuit degrades at higher comparison
frequencies. To compensate for this, the DIV4 word should
be set to one if the comparison frequency exceeds 20 MHz.
Don't care
CLKoutX
_EN bit
1
0
1
Enable
10 ns
ε
EN_CLKout
_Global bit
Don't care
1
0
1
bits
(CLKoutX_EN)
Don't care
Don't care
High / No
GOE pin
Connect
Low
20 ns
δ
Output State
CLKoutX
Enabled
and
Figure
Low
Off
Off
2.
the
13
The function of this word is to divide the comparison frequen-
cy presented to the lock detect circuit by 4.
FIGURE 2. Digital Lock Detect Flowchart
20211405
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