SST25VF512-20-4C-SA Microchip Technology, SST25VF512-20-4C-SA Datasheet - Page 12

Flash 64K X 8 14 us

SST25VF512-20-4C-SA

Manufacturer Part Number
SST25VF512-20-4C-SA
Description
Flash 64K X 8 14 us
Manufacturer
Microchip Technology
Datasheet

Specifications of SST25VF512-20-4C-SA

Memory Type
NAND
Memory Size
512 Kbit
Architecture
Sectored
Interface Type
SPI
Access Time
20 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Current
10 mA
Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Organization
64 KB x 8
Lead Free Status / Rohs Status
No RoHS Version Available

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Data Sheet
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE# must be driven high
before the WREN instruction is executed.
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. CE# must be driven high before
the WRDI instruction is executed.
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Enable-Write-
Status-Register instruction does not have any effect and
will be wasted, if it is not followed immediately by the Write-
©2005 Silicon Storage Technology, Inc.
FIGURE 11: W
FIGURE 12: W
RITE
RITE
E
D
NABLE
ISABLE
(WREN) S
(WRDI) S
SCK
CE#
SCK
CE#
SO
SO
SI
SI
EQUENCE
EQUENCE
MODE 3
MODE 0
MODE 3
MODE 0
HIGH IMPEDANCE
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
MSB
0 1 2 3 4 5 6 7
12
Status-Register (WRSR) instruction. CE# must be driven
low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
04
06
1192 F36.6
1192 F35.6
512 Kbit SPI Serial Flash
SST25VF512
S71192-08-000
11/05

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