PDIUSBD12D NXP Semiconductors, PDIUSBD12D Datasheet - Page 8

• Manufacturer Part Number: PDIUSBD12D
• Description: USB Interface IC USB INTRFC W/PARL BUS
• Manufacturer: NXP Semiconductors

Specifications of PDIUSBD12D

• Operating Supply Voltage: 4 V to 5.5 V
• Lead Free Status / Rohs Status: Details
• Other names: PDIUSBD12D,112

Philips Semiconductors
PDIUSBD12_9
Product data sheet
6.10 Example of parallel interface to an 80C51 microcontroller
6.7 GoodLink
6.8 Memory Management Unit (MMU) and integrated RAM
6.9 Parallel and DMA interface
A good USB connection indication is provided through the GoodLink technology. During
enumeration, the LED indicator will momentarily blink on corresponding to the
enumeration traffic. When the PDIUSBD12 is successfully enumerated and configured,
the LED indicator will be permanently on. Subsequent successful (with acknowledgment)
transfer to and from the PDIUSBD12 will blink off the LED. During suspend, the LED will
be off.
This feature provides a user-friendly indication on the status of the USB device, the
connected hub and the USB traffic. It is a useful field diagnostics tool to isolate faulty
equipment. This feature helps lower field support and hotline costs.
The difference between MMU and the integrated RAM buffer lies in the speed between
USB, running in bursts of 12 Mbit/s and the parallel interface to the microcontroller. This
allows the microcontroller to read and write USB packets at its own speed.
A generic parallel interface is defined for ease-of-use and speed, and allows direct
interfacing to major microcontrollers. To a microcontroller, the PDIUSBD12 appears as a
memory device with 8-bit data bus and 1-bit address line (occupying two locations). The
PDIUSBD12 supports both multiplexed and non-multiplexed address and data bus. The
PDIUSBD12 also supports Direct Memory Access (DMA) transfer that allows the main
endpoint (endpoint 2) to directly transfer to and from the local shared memory. Both
single-cycle and burst mode DMA transfers are supported.
In the example shown in
separate address and data bus configuration. The A0 pin of the PDIUSBD12 connects to
any of the 80C51 I/O ports. This port controls the command or data phase to the
PDIUSBD12. The multiplexed address and data bus of the 80C51 can now be directly
connected to the data bus of the PDIUSBD12. The address phase will be ignored by the
PDIUSBD12. The clock input signal of the 80C51 (pin XTAL1) can be provided by output
CLKOUT of the PDIUSBD12.
Fig 3. Example of a parallel interface to an 80C51 microcontroller
PDIUSBD12
DATA [ 7:0 ]
CLKOUT
Rev. 09 — 11 May 2006
INT_N
WR_N
RD_N
CS_N
Figure
ALE
A0
3, the ALE pin is permanently tied to LOW to signify a
USB peripheral controller with parallel bus
INTO/P3.2
ANY I/O PORT (for example, P3.3)
P [ 0.7:0.0 ] /AD [ 7:0 ]
WR/P3.6
RD/P3.7
XTAL1
ANY I/O PORT
80C51
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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