74ABT899D NXP Semiconductors, 74ABT899D Datasheet - Page 4

Bus Transceivers 9-BIT LATCH XCVR W/PARITY 3-S

74ABT899D

Manufacturer Part Number
74ABT899D
Description
Bus Transceivers 9-BIT LATCH XCVR W/PARITY 3-S
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74ABT899D

Logic Type
BiCMOS
Logic Family
ABT
Number Of Channels Per Chip
8
Input Level
TTL
Output Level
TTL
Output Type
3-State
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Propagation Delay Time
4.5 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 85 C
Package / Case
SOP-28
Function
Latched Transceiver with Parity Checker
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Circuits
1
Polarity
Non-Inverting
Lead Free Status / Rohs Status
 Details
Other names
74ABT899D,112

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74ABT899D
Manufacturer:
INTERSIL
Quantity:
81
Philips Semiconductors
FUNCTION TABLE
H = High voltage level
L = Low voltage level
X = Don’t care
1998 Jan 16
OEB
EVEN
APAR
ODD/
OEA
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
H
H
H
H
H
H
LEA
SEL
L
L
L
L
L
L
A0
A1
A2
A3
A4
A5
A6
A7
10
12
13
16
11
OEA
3
4
5
6
7
8
9
1
H
H
H
H
H
H
L
L
L
L
L
L
INPUTS
SEL
H
H
H
H
X
L
L
L
L
L
L
X
LEA
X
H
X
X
H
H
H
H
H
X
L
L
LEB
LE
H
H
H
H
H
H
X
L
X
X
L
X
Transparent
OE
Latch
Output
9–bit
Buffer
9–bit
3-State A bus and B bus (input A & B simultaneously)
B
B
B
B
B
A
A
A
A
A
Output to A bus and B bus (NOT ALLOWED)
A, transparent B latch, generate parity from B0 - B7, check B bus parity
A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
A, transparent B latch, parity feed-through, check B bus parity
A, transparent A & B latch, parity feed-through, check A & B bus parity
B, transparent A latch, generate parity from A0 - A7, check A bus parity
B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
B, transparent A latch, parity feed-through, check A bus parity
B, transparent A & B latch, parity feed-through, check A & B bus parity
Generator
Parity
mux
1
0
4
Generator
Parity
OPERATING MODE
1
0
mux
Transparent
Latch
9–bit
Output
Buffer
9–bit
OE
LE
74ABT899
Product specification
27
26
25
24
23
22
21
20
19
18
17
15
2
SA00292
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
ERRA
ERRB
OEB
LEB

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