UCN5833EP Allegro, UCN5833EP Datasheet - Page 5

• Manufacturer Part Number: UCN5833EP
• Description: BiMOS BIT Serial Input Latched Driver 44-Pin PLCC
• Manufacturer: Allegro

Specifications of UCN5833EP

• Package: 44PLCC
• Operating Temperature: -20 to 85 °C

5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
STROBE
OUTPUT
ENABLE
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
DATA IN
A. Minimum Data Active Time Before Clock Pulse
B. Minimum Data Active Time After Clock Pulse
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE tied
high) will require that the OUTPUT ENABLE input be low during serial
data entry.
are disabled (OFF) without affecting the information stored in the
latches or shift register. With the OUTPUT ENABLE input high, the
outputs are controlled by the state of the latches.
CLOCK
OUT
Serial Data present at the input is transferred to the shift register
Information present at any register is transferred to its respective
When the OUTPUT ENABLE input is low, all of the output buffers
(Data Set-Up Time) .......................................................................... 75 ns
(Data Hold Time) ............................................................................. 75 ns
Output Transition ........................................................................... 500 ns
N
A
C
B
D
E
F
G
Dwg. No. A-12,276A