CS4299-JQ Cirrus Logic Inc, CS4299-JQ Datasheet - Page 16

• Manufacturer Part Number: CS4299-JQ
• Description: Audio Codec 1ADC / 1DAC 18-Bit/20-Bit 48-Pin LQFP
• Manufacturer: Cirrus Logic Inc
• Type: PCMr

Specifications of CS4299-JQ

• Package: 48LQFP
• Adc/dac Resolution: 18/20 Bit
• Number Of Channels: 1ADC /1 DAC
• Sampling Rate: 48 KSPS
• Number Of Adc Inputs: 8
• Number Of Dac Outputs: 3
• Number Of Dacs: 1
• Operating Supply Voltage: 3.3|5 V

3.2
In the serial data input frame, data is passed on the SDATA_IN pin from the CS4299 to the AC ’97 con-
troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 13 illus-
trates the serial port timing.
The PCM capture data from the CS4299 is shifted out MSB first in the most significant 18 bits of each slot.
The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the AC ’97
Controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun-
cate) to the desired bit depth.
Bits that are reserved or not implemented in the CS4299 will always be returned ‘cleared’.
3.2.1 Serial Data Input Slot Tag Bits (Slot 0)
Codec Ready
Slot 1 Valid
Slot 2 Valid
Slot [3:10] Valid
3.2.2 Status Address Port (Slot 1)
RI[6:0]
SR[3:10]
16
16
Codec
Ready
Bit 19
Bit 15
0
RI6
18
AC-Link Audio Input Frame
Slot 1
Valid
14
RI5
17
Slot 2
Valid
13
RI4
16
CS4299 ADCs. Only if a Slot [3:10] Valid bit is ‘set’ will the corresponding input slot contain
valid data.
Slot 3
The Codec Ready bit indicates the readiness of the CS4299 AC-link. Immediately after a Cold
Reset this bit will be ‘clear’. Once the CS4299 clocks and voltages are stable, this bit will be
‘set’. Until the Codec Ready bit is ‘set’, no AC-link transactions should be attempted by the
controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any
other analog function. Those must be checked in the Powerdown Control/Status Register (In-
dex 26h) by the controller before any access is made to the mixer registers. Any accesses to
the CS4299 while Codec Ready is ‘clear’ are ignored.
When ‘set’, the Slot 1 Valid bit indicates Slot 1 contains a valid read back address.
When ‘set’, the Slot 2 Valid bit indicates Slot 2 contains valid register read data.
When ‘set’, the Slot [3:10] Valid bits indicate Slot [3:10] contains valid capture data from the
Register Index. The RI[6:0] bits echo the AC ’97 register address when a register read has
been requested in the previous frame. The CS4299 will only echo the register index for a read
access. Write accesses will not return valid data in Slot 1.
Slot Request. If SRx is ‘set’, this indicates the CS4299 SRC does not need a new sample on
the next AC-link frame for that particular slot. If SRx is ‘clear’, the SRC indicates a new sample
is needed on the following frame. If the VRA bit in the Extended Audio Status/Control Register
(Index 2Ah) is ‘clear’, the SR[3:10] bits are always 0. When VRA is ‘set’, the SRC is enabled
and the SR[3:10] bits are used to request data.
Valid
12
RI3
15
Slot 4
RI2
Valid
14
11
RI1
13
Slot 5
Valid
10
RI0
12
Slot 6
Valid
9
SR3 SR4 SR5 SR6 SR7 SR8 SR9 SR10
11
Slot 7
Valid
8
10
Slot 8
Valid
9
7
8
Slot 9
Valid
6
7
Slot 10
Valid
5
6
4
0
5
4
3
0
0
3
2
0
2
CS4299
Reserved
CS4299
1
0
DS319PP6
1
0
0
0