CY7C1018V33-12VC Cypress Semiconductor Corp, CY7C1018V33-12VC Datasheet

no-image

CY7C1018V33-12VC

Manufacturer Part Number
CY7C1018V33-12VC
Description
SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 12ns 32-Pin SOJ
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1018V33-12VC

Package
32SOJ
Timing Type
Asynchronous
Density
1 Mb
Typical Operating Supply Voltage
3.3 V
Address Bus Width
17 Bit
Number Of I/o Lines
8 Bit
Number Of Ports
1
Number Of Words
128K
3
Features
Functional Description
The CY7C1018V33/CY7C1019V33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE), an active LOW Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
Selection Guide
Cypress Semiconductor Corporation
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
• High speed
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
Logic Block Diagram
WE
CE
OE
— t
A
A
A
A
A
A
A
A
A
AA
0
1
2
3
4
5
6
7
8
= 10 ns
INPUT BUFFER
512 x 256 x 8
DECODER
COLUMN
ARRAY
POWER
DOWN
3901 North First Street
L
7C1019V33-10
175
pins (I/O
fied on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018V33 is available in a standard 300-mil-wide
SOJ and CY7C1019V33 is available in a standard
400-mil-wide
CY7C1019V33 are functionally equivalent in all other re-
spects.
10
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1019V33–1
0
1
2
3
4
5
6
7
0
through I/O
San Jose
package.
7C1018V33-12
7C1019V33-12
I/O
I/O
V
V
I/O
I/O
128K x 8 Static RAM
WE
CE
CC
A
A
A
A
A
A
A
A
SS
7
7
) is then written into the location speci-
0
1
2
0
1
2
3
4
5
6
3
160
0.5
Pin Configurations
12
5
0
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
through A
CA 95134
Top View
The
0
SOJ
through I/O
CY7C1018V33
CY7C1019V33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CY7C1018V33
16
).
7C1018V33-15
7C1019V33-15
October 18, 1999
7
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
) are placed in a
SS
CC
16
15
14
13
12
11
10
9
8
408-943-2600
145
7
6
5
4
0.5
15
5
1019V33–2
and

Related parts for CY7C1018V33-12VC

CY7C1018V33-12VC Summary of contents

Page 1

... The eight input/output pins (I/O high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1018V33 is available in a standard 300-mil-wide SOJ and CY7C1019V33 is available in a standard 400-mil-wide CY7C1019V33 are functionally equivalent in all other re- spects ...

Page 2

... IH V < MAX Max > V – 0.3V > V – 0.3V < 0.3V Test Conditions T = 25° MHz 5. CY7C1018V33 CY7C1019V33 Ambient [2] Temperature V 0°C to +70°C 3.3V 7C1018V33-12 7C1018V33-15 7C1019V33-12 7C1019V33-15 Max. Min. Max. Min. Max. 2.4 2.4 0.4 0.4 0.4 V 2 ...

Page 3

... R1 480 3.3V 3.0V R2 GND 5 pF 255 INCLUDING JIG AND SCOPE (b) 1019V33–3 7C1019V33-10 Min. Max less than less than t , and t HZCE LZCE HZOE LZOE HZWE 3 CY7C1018V33 CY7C1019V33 ALL INPUT PULSES 90% 90% 10 1019V33–4 7C1018V33-12 7C1018V33-15 7C1019V33-12 7C1019V33-15 Min. Max. Min. Max ...

Page 4

... No input may exceed 2.0V > V – 0.3V > V – 0. DATA RETENTION MODE 3.0V V > CDR OHA DOE DATA VALID 50 CY7C1018V33 CY7C1019V33 Min. Max + 0.5V 2.0 CC 150 0 < 1019V33–5 DATA VALID 1019V33–6 t HZOE t HZCE HIGH IMPEDANCE t PD 50% 1019V33–7 Unit ICC ...

Page 5

... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 14. During this period the I/Os are in the output state and input signals should not be applied SCE SCE PWE t SD DATA VALID [12, 13 SCE PWE t SD DATA VALID IN 5 CY7C1018V33 CY7C1019V33 1019V33– 1019V33–98 ...

Page 6

... DATA I/O t HZWE Truth Table I High High Data Out Data High Z Ordering Information Speed (ns) Ordering Code 12 CY7C1018V33-12VC CY7C1018V33L-12VC 15 CY7C1018V33-15VC CY7C1018V33L-15VC 10 CY7C1019V33-10VC 12 CY7C1019V33-12VC CY7C1019V33L-12VC 15 CY7C1019V33-15VC CY7C1019V33L-15VC Document #: 38–00637–B [13 SCE PWE t SD DATA VALID –I/O Mode 7 Power-Down Power-Down Read Write Selected, Outputs Disabled ...

Page 7

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 32-Lead (300-Mil) Molded SOJ V32 32-Lead (400-Mil) Molded SOJ V33 CY7C1018V33 CY7C1019V33 51-85041-A 51-85033-A ...

Related keywords