XC3190A-4PQ160C Xilinx Inc, XC3190A-4PQ160C Datasheet - Page 5

• Manufacturer Part Number: XC3190A-4PQ160C
• Description: FPGA XC3100A Family 6K Gates 320 Cells 227MHz CMOS Technology 5V 160-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC3190A-4PQ160C

• Package: 160PQFP
• Family Name: XC3100A
• Device Logic Units: 320
• Device System Gates: 6000
• Number Of Registers: 928
• Maximum Internal Frequency: 227 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 138
• Ram Bits: 64160
• Re-programmability Support: Yes
• Case: QFP160
• Dc: 98+

Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and con-
trols one program selection in the Field Programmable
Gate Array.
The memory cell outputs Q and Q use ground and V
els and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
November 9, 1998 (Version 3.1)
Read or
Figure 4: Input/Output Block.
Each IOB includes input and output storage elements and I/O options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable.
A clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.
Write
Data
(OUTPUT ENABLE)
REGISTERED IN
R
DIRECT IN
3- STATE
OUT
PROGRAM
CONTROLLED
MULTIPLEXER
T
O
I
Q
INVERT
OUT
OK
Q
Q
PROGRAM-CONTROLLED MEMORY CELLS
Configuration
Control
3-STATE
INVERT
IK
=
X5382
CC
PROGRAMMABLE INTERCONNECTION POINT or PIP
LATCH
D
Q
FLOP
FLOP
FLIP
FLIP
R
or
R
lev-
Q
D
XC3000 Series Field Programmable Gate Arrays
OUTPUT
SELECT
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing infor-
mation, embedded in the program data by the development
system, to direct memory-cell loading. The serial-data
framing and length-count preamble provide programming
compatibility for mixes of various FPGA device devices in a
synchronous, serial, daisy-chain fashion.
I/O Block
Each user-configurable IOB shown in
interface between the external package pin of the device
and the internal user logic. Each IOB includes both regis-
tered and direct input paths. Each IOB provides a program-
mable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each IOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.
THRESHOLD
TTL or
CMOS
INPUT
SLEW
RATE
OUTPUT
BUFFER
PASSIVE
PULL UP
(GLOBAL RESET)
CK1
CK2
Vcc
Figure
I/O PAD
X3029
4, provides an
7-7
7