CY7B991V-2JCT Cypress Semiconductor Corp, CY7B991V-2JCT Datasheet - Page 8

• Manufacturer Part Number: CY7B991V-2JCT
• Description: Zero Delay Programmable PLL Clock Buffer Single 15MHz to 80MHz 32-Pin PLCC T/R
• Manufacturer: Cypress Semiconductor Corp
• Type: Zero Delay Programmable PLL Clock Bufferr

Specifications of CY7B991V-2JCT

• Package: 32PLCC
• Number Of Elements Per Chip: 1
• Output Frequency Range: 3.75 to 80 MHz
• Operating Temperature: 0 to 70 °C
• Operating Supply Voltage: 3.3 V

Figure 9
downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)
necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulate
low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a
series.
Document Number: 38-07141 Rev. *G
shows the CY7B991V connected in series to construct a zero skew clock distribution tree between boards. Delays of the
SYSTEM
CLOCK
DISTRIBUTION
20 MHz
CLOCK
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
FB
REF
FS
Figure 9. Board-to-Board Clock Distribution
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Figure 8. Multi-Function Clock Driver
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
REF
L4
SKEWED –3.125 ns (–4t
L1
L2
80 MHz
L3
Z
ZERO SKEW
0
INVERTED
80 MHz
20 MHz
80 MHz
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Z
Z
Z
0
U
0
0
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
)
Z
0
Z
Z
0
Z
0
0
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CY7B991V
Page 8 of 17
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