DS90C383MTDX National Semiconductor, DS90C383MTDX Datasheet - Page 13

• Manufacturer Part Number: DS90C383MTDX
• Description: LVDS Flat Panel Display 0.45V 56-Pin TSSOP T/R
• Manufacturer: National Semiconductor

Specifications of DS90C383MTDX

• Package: 56TSSOP
• Number Of Elements Per Chip: 4
• Transmission Data Rate: 1800 Mbps
• Differential Input Low Threshold Voltage: -0.1 V
• Differential Input High Threshold Voltage: 0.1 V
• Typical Operating Supply Voltage: 3.3 V

TxIN
TxOUT+
TxOUT−
FPSHIFT IN
R_FB
RTxCLK OUT+
TxCLK OUT−
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
TxIN
TxOUT+
TxOUT−
TxCLKIN
TxCLK OUT+
TxCLK OUT−
PWR DWN
R_FB
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
NC
DS90C383 TSSOP Package Pin Description — FPD Link Transmitter
DS90C383SLC SLC64A (FBGA) Package Pin Summary — FPD Link
Transmitter
DS90C383SLC SLC64A (FBGA) Package Pin Description — FPD Link
Transmitter
CC
CC
Pin Name
Pin Name
Pin
A1
A2
A3
A4
A5
A6
CC
CC
CC
CC
I/O
TxCLKOUT-
I/O
LVDS VCC
LVDS VCC
O
O
O
O
Pin Name
O
O
O
O
I
I
I
I
I
I
I
I
I
I
TxOUT0+
TxOUT0-
I
I
I
I
I
I
I
I
I
I
TxIN27
By Pin
No.
28
No.
4
4
1
1
1
1
1
3
4
1
2
1
3
28
4
4
1
1
1
1
1
3
5
1
2
2
4
6
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
Programmable strobe select.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
TTL level input.
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL IeveI clock input. The rising edge acts as data strobe. Pin name TxCLK IN.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at
power down.
Programmable strobe select. HIGH = rising edge, LOW = falling edge.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
Pins not connected.
Type
O
O
O
P
P
I
13
Description
Description
Pin
G1
G6
D3
E4
E8
B3
LVDS GND
By Pin Type
Pin Name
GND
GND
GND
GND
GND
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Type
G
G
G
G
G
G