CY7C1302CV25-167BZC Cypress Semiconductor Corp, CY7C1302CV25-167BZC Datasheet
CY7C1302CV25-167BZC
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CY7C1302CV25-167BZC Summary of contents
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... K clock. QDR has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Accesses to the CY7C1302CV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K) ...
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... Selection Guide Maximum Operating Frequency Maximum Operating Current Pin Configuration–CY7C1302CV25 (Top View Gnd/144M NC/36M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H NC VREF VDDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK ...
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... K). Read Operations The CY7C1302CV25 is organized internally as 2 arrays of 256K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K) ...
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... This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1302CV25 can be used with a single clock mode. In this mode the device will recognize only the pair of input clocks (K and K) that control both the input and output registers ...
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... During the Data portion of a Write sequence, only the byte (D D remains unaltered. [8:0] No data is written into the device during this portion of a Write operation. No data is written into the device during this portion of a Write operation. ↑ represents rising edge. , BWS 0 CY7C1302CV25 RPS WPS D(A+0)at K(t) ↑ Q(A+0) at C(t+1)↑ ...
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... RQ <= 350Ω. DDQ /2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω. DDQ (Max – 0.2V. IL REF (Max.) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1302CV25 Ambient [10] Temperature ( 0°C to +70°C 2.5 ± 0.1V Min. Typ. Max. ...
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... JIG AND SCOPE [17] Description , BWS ) 0 1 Set-up to Clock (K and K) Rise /I and load capacitance shown in ( test loads the time power needs to be supplied above V Power CY7C1302CV25 165 FBGA Package Unit 16.7 2.5 Test Conditions T = 25° MHz 2.5V 1.5V DDQ ALL INPUT PULSES 1 ...
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... PREMILINARY [17] Description , BWS ) 0 1 Hold after Clock (K and K) Rise [19, 20] [19, 20] is less than t and, t less than t . CLZ CHZ CO CY7C1302CV25 -167 -133 -100 Min. Max. Min. Max. Min. Max. 0.7 0.8 1.0 0.7 0.8 1.0 0.7 0.8 1.0 2.5 3.0 3.0 1.2 1 ...
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... In this example, if address A2=A1 then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results.This note applies to the whole diagram. Document #: 38-05491 Rev. *A PREMILINARY WRITE READ WRITE CYC t KHKH tHC D31 D50 D51 Q00 Q01 t DOH t CLZ KHKH tCYC CY7C1302CV25 NOP WRITE D60 D61 Q20 Q21 Q40 t DOH DON’T CARE NOP 9 10 Q41 t CHZ UNDEFINED Page ...
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... The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction CY7C1302CV25 Page ...
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... Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1302CV25 Page ...
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... TEST-LOGIC/ 0 IDLE Note: 24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05491 Rev. *A PREMILINARY [24] SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE- EXIT2-DR 1 UPDATE- CY7C1302CV25 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... TAP Controller [11, 9, 25] Over the Operating Range Test Conditions = −2 −100 µ 2 100 µ GND ≤ V ≤ DDQ [26, 27] Over the Operating Range Description CY7C1302CV25 0 Selection 0 Circuitry 0 0 Min. Max. 1.7 2.1 0.7 0.2 1 0.3 DD –0.3 0.7 –5 5 Min. Max. 100 ...
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... TH t TMSS t TMSH t TDIS t TDIH t TDOX Value CY7C1302CV25 001 Version number. 01011010010010110 Defines the type of SRAM. 00000110100 Allows unique identification of SRAM vendor. 1 Indicate the presence register. CY7C1302CV25 [26, 27] Min. Max ALL INPUT PULSES 2.5V 1.25V t TCYC t TDOV Description Page Unit ns ns ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Boundary Scan Order Bump 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K CY7C1302CV25 Description (continued) Bit # Bump 10J 26 11J 27 11H 28 10G 11F 31 11G 10F ...
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... Boundary Scan Order (continued) Bit # Document #: 38-05491 Rev. *A PREMILINARY Boundary Scan Order Bump ID Internal CY7C1302CV25 (continued) Bit # Bump 100 1P 101 3R 102 4R 103 4P 104 5P 105 5N 106 5R Page ...
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... Ordering Information Speed (MHz) Ordering Code 167 CY7C1302CV25-167BZC 133 CY7C1302CV25-133BZC 100 CY7C1302CV25-100BZC Package Diagram Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC and Samsung. All product and company names mentioned in this document are trademarks of their respective holders. ...
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... Document History Page Document Title:CY7C1302CV25 9-Mb Burst of 2 Pipelined SRAM with QDR™ Architecture Document Number: 38-05491 REV. ECN NO. Issue Date ** 208401 see ECN *A 230396 see ECN Document #: 38-05491 Rev. *A PREMILINARY Orig. of Change DIM New Data Sheet VBL Upload datasheet to the internet ...