XC3S500E-4FG320C Xilinx Inc, XC3S500E-4FG320C Datasheet - Page 84

• Manufacturer Part Number: XC3S500E-4FG320C
• Description: FPGA Spartan-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 320-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S500E-4FG320C

• Package: 320FBGA
• Family Name: Spartan-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 232
• Ram Bits: 368640

Functional Description
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in
serial Flash PROM is supported in Stepping 1 devices. It is
not supported in Stepping 0 devices. Use SPI Flash mode
(M[2:0] = <0:0:1>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
Programming Support
For successful daisy-chaining, the DONE_cycle configura-
tion option must be set to cycle 5 or sooner. The default
cycle is 4. See
tional information.
ally pre-programmed before it is mounted on the printed cir-
cuit board. The
industry-standard programming files that can be used with
third-party gang programmers. Consult your specific SPI
Flash vendor for recommended production programming
solutions.
In-system programming support is available from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the SPI Flash signals,
84
I
Recommend
open-drain
In production applications, the SPI Flash PROM is usu-
PROG_B
driver
TMS
TCK
TDO
TDI
+2.5V
JTAG
Variant Select
Figure
Table 69
SPI Mode
Xilinx ISE development software
S
‘0’
‘0’
‘1’
‘1’
‘1’
P
57. Daisy-chaining from a single SPI
HSWAP
M2
M1
M0
VS2
VS1
VS0
TDI
TMS
TCK
PROG_B
!
and the
SPI-based daisy-chaining is
only supported in Stepping 1.
Spartan-3E
Figure 57: Daisy-Chaining from SPI Flash Mode (Stepping 1)
VCCINT
FPGA
+1.2V
GND
Start-Up
VCCAUX
VCCO_0
VCCO_2
CSO_B
INIT_B
DOUT
DONE
CCLK
MOSI
TDO
DIN
section for addi-
VCCO_0
+3.3V
+2.5V
produces
I
www.xilinx.com
W
‘1’
P
+2.5V
DATA_IN
DATA_OUT
SELECT
WR_PROTECT
HOLD
CLOCK
FPGA—the FPGA on the left in the diagram—finishes load-
ing its configuration data from the SPI Flash PROM, the
master device uses its DOUT output pin to supply data to
the next device in the daisy-chain, on the falling CCLK edge.
Design Note
SPI mode daisy chains are supported only in Stepping 1 sil-
icon versions.
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the SPI Flash, in high-impedance (Hi-Z). If the
HSWAP input is Low, the I/Os have pull-up resistors to the
V
gramming hardware then has direct access to the SPI Flash
pins. The programming access points are highlighted in the
gray box in
Beginning with the Xilinx ISE 8.2i software release, the
iMPACT programming utility provides direct, in-system pro-
totype programming support for STMicro M25P-series SPI
serial Flash PROMs and the Atmel AT45DB-series Data
Flash PROMs using the
IV, or other compatible programming cable.
+3.3V
CCO
GND
VCC
Serial
Flash
+3.3V
SPI
input on their respective I/O bank. The external pro-
Figure
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
53,
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
Figure
Platform Cable
Spartan-3E
VCCINT
FPGA
+1.2V
GND
54, and
DS312-2 (v3.8) August 26, 2009
VCCAUX
VCCO_0
VCCO_2
INIT_B
DONE
DOUT
TDO
Figure
Product Specification
USB,
VCCO_0
+3.3V
+2.5V
57.
DS312-2_48_082009
Xilinx Parallel
CCLK
DOUT
PROG_B
TCK
TMS
DONE
INIT_B
R