89TTM553BL Integrated Device Technology (Idt), 89TTM553BL Datasheet - Page 7

• Manufacturer Part Number: 89TTM553BL
• Description: ATM Traffic Management 10Gbps 1.8V 960-Pin FCBGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 89TTM553BL

• Package: 960FCBGA
• Traffic Class: VBR
• Throughput: 10000 Mbps
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.71 V
• Maximum Operating Supply Voltage: 1.89 V

IDT 89TTM553
HT_CLK_CP, HT_CLK_CN
HT_CLK_KP,
HT_CLK_KN
HT_ADDR[19:0]
HT_RD_N
HT_DIN[35:0]
HT_WR_N
HT_DOUT[35:0]
HT_VREF[1:0]
LLT_CLK_CP,
LLT_CLK_CN
LLT_CLK_KP,
LLT_CLK_KN
LLT_ADDR[19:0]
LLT_RD_N
LLT_DIN[10:0]
LLT_WR_N
LLT_DOUT[10:0]
Signal Name
Signal Name
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
0.75V
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
I/O Type
I/O Type
Table 7 Linked List Table QDR SRAM
Table 6 Head Tail QDR SRAM
Dir.
Dir.
—
O
O
O
O
O
O
O
O
O
O
I
I
I
I
7 of 30
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
Freq.
Freq.
—
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
HT QDR SRAM output clock: This clock pair times the control
outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
HT QDR SRAM address outputs.
asserted, a read cycle is initiated to the external QDR SRAM
devices.
hold times around the rising edges of C and C# during read
operations.
asserted, a write cycle is initiated to the external QDR SRAM
devices.
nized to the K and K# during write operations.
HSTL reference. Nominally V
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
LLT QDR SRAM output clock: This clock pair times the control
outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
asserted, a read cycle is initiated to the external QDR SRAM
devices.
hold times around the rising edges of C and C# during read
operations.
asserted, a write cycle is initiated to the external QDR SRAM
devices.
nized to the K and K# during write operations.
HT QDR SRAM input clock: This clock pair registers data
HT QDR SRAM synchronous read output (active low): When
HT QDR SRAM data inputs: Input data must meet setup and
HT QDR SRAM synchronous write output (active low): When
HT QDR SRAM write data outputs: Output data is synchro-
LLT QDR SRAM input clock: This clock pair registers data
LLT QDR SRAM address outputs.
LLT QDR SRAM synchronous read output (active low): When
LLT QDR SRAM data inputs: Input data must meet setup and
LLT QDR SRAM synchronous write output (active low): When
LLT QDR SRAM write data outputs: Output data is synchro-
Remarks
Remarks
DDQ
/ 2, so connect to 0.75 V
March 3, 2005