CY7C1049B-12VXC Cypress Semiconductor Corp, CY7C1049B-12VXC Datasheet - Page 4

• Manufacturer Part Number: CY7C1049B-12VXC
• Description: SRAM Chip Async Single 5V 4M-Bit 512K x 8 12ns 36-Pin SOJ
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1049B-12VXC

• Package: 36SOJ
• Timing Type: Asynchronous
• Density: 4 Mb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 19 Bit
• Number Of I/o Lines: 8 Bit
• Number Of Ports: 1
• Number Of Words: 512K

Document #: 38-05169 Rev. *B
Data Retention Characteristics
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
V
I
t
t
Notes:
Parameter
Parameter
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
10. t
11. No input may exceed V
CCDR
CDR
R
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
6. t
7. At any given temperature and voltage condition, t
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
DR
[10]
I
is started.
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
OL
HZOE
r
[3]
< 3 ns for all the speeds
/I
OH
, t
and 30-pF load capacitance.
HZCE
[8, 9]
, and t
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
V
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CC
CC
HZWE
(typical) to the First Access
for Data Retention
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
CC
+ 0.5V.
Description
[7]
[7]
[6, 7]
[7]
[6, 7]
[6, 7]
Description
Over the Operating Range
Over the Operating Range
HZCE
[5]
is less than t
Com’l
LZCE
, t
HZOE
[4]
Min.
12
12
10
10
10
is less than t
1
3
0
3
0
0
0
7
0
3
L V
-12
CE > V
V
CC
IN
Max.
LZOE
12
12
12
> V
6
6
6
6
= V
power
, and t
HZWE
CC
CC
DR
time has to be provided initially before a read/write operation
Conditions
– 0.3V
– 0.3V or V
HZWE
and t
= 2.0V,
Min.
15
15
12
12
12
1
3
0
3
0
0
0
8
0
3
is less than t
SD
.
-15
[11]
Max.
IN
15
15
15
LZWE
7
7
7
7
< 0.3V
for any given device.
Min.
17
17
12
12
12
1
3
0
3
0
0
0
8
0
3
Min.
CY7C1049B
t
2.0
RC
0
-17
Max.
17
17
17
8
7
7
8
Max.
200
Page 4 of 9
Unit
ms
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µA
ns
ns
V
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