XC3142A-3PQ100I Xilinx Inc, XC3142A-3PQ100I Datasheet - Page 32

• Manufacturer Part Number: XC3142A-3PQ100I
• Description: FPGA XC3100A Family 3K Gates 144 Cells 270MHz CMOS Technology 5V 100-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC3142A-3PQ100I

• Package: 100PQFP
• Family Name: XC3100A
• Device Logic Units: 144
• Device System Gates: 3000
• Number Of Registers: 480
• Maximum Internal Frequency: 270 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 82
• Ram Bits: 30784
• Re-programmability Support: Yes

XC3000 Series Field Programmable Gate Arrays
General XC3000 Series Switching Characteristics
Notes: 1. At power-up, V
7-34
DONE/PROG
PWRDWN (3) Power Down V
RESET (2)
DONE/PROG
V
M0/M1/M2
PWRDWN
CC
(Output)
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
3. PWRDWN transitions must occur while V
RESET
(Valid)
holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a
non-monotonically rising V
after Vcc has reached 4.0 V (2.5 V for XC3000L).
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
INIT
Description
M0, M1, M2 setup time required
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
Width (Low) required for Re-config.
INIT response after D/P is pulled Low
User State
CC
must rise from 2.0 V to V
2 T
MR
CC
CC
5 T
may require a >1- s High level on RESET, followed by a >6- s Low level on RESET and D/P
PGW
6 T
PGI
CC
CC
3 T
>4.0 V(2.5 V for XC3000L).
min in less than 25 ms. If this is not possible, configuration can be delayed by
RM
Clear State
2
3
4
5
6
Symbol
V
T
T
4 T
T
T
T
CCPD
MRW
PGW
PGI
MR
RM
MRW
Min
4.5
2.3
November 9, 1998 (Version 3.1)
1
6
6
Configuration State
Note 3
Max
7
V
CCPD
Units
X5387
V
s
s
s
s
s
R