PI3VDP101LSZDEX Pericom Semiconductor, PI3VDP101LSZDEX Datasheet - Page 8

• Manufacturer Part Number: PI3VDP101LSZDEX
• Manufacturer: Pericom Semiconductor

Specifications of PI3VDP101LSZDEX

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Differential Input Characteristics for IN_D and RX_IN signals
Symbol
Tbit
V
T
V
Z
V
Z
RX-EYE
RX-DC
RX-HIGH-Z
RX-DIFFp-p
CM-AC-pp
RX-Bias
09-0021
Parameter
Unit Interval
Differential Input Peak
to Peak Voltage
Minimum Eye Width at
IN_D input pair
AC Peak
Common Mode Input
Voltage
0.175
Min
360
100
0.8
40
0
Nom
50
Shifter with Integrated I
8
1.200
Max
100
2.0
60
Dual Mode DisplayPort™ to HDMI™ Level
Units
Tbit
mV
kΩ
ps
Ω
V
V
Comments
Tbit is determined by the display
mode. Nominal bit rate ranges
from 250Mbps to 2.5Gbps per lane.
Nominal Tbit at 2.5 Gbps=400ps.
360ps=400ps-10%
VRX-DIFFp-p=2'|VRX-D+ x
VRX-D-|
Applies to IN_D and RX_IN signals
The level shifter may add a maximum
of 0.02UI jitter
VCM-AC-pp = |VRX-D+
+ VRX-D-|/2 - VRX-CM-DC.
VRX-CM-DC = DC(avg) of|VRX-D+
+ VRX-D-|/2
VCM-AC-pp includes all frequencies
above 30 kHz.
Required IN_D+ as well as IN_D- DC
impedance (50Ω ± 20% tolerance).
Intended to limit power-up stress on
chipset's PCIE output buffers.
Differential inputs must be in a high
impedance state when OE# is HIGH.
2
C ID for HDMI™ Detection
PS8955B
PI3VDP101LS
11/17/09