AD7280AWBSTZ Analog Devices Inc, AD7280AWBSTZ Datasheet - Page 6

• Manufacturer Part Number: AD7280AWBSTZ
• Description: IC BATT MON LI-ION AUTO 48LQFP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of AD7280AWBSTZ

• Function: Battery Monitor, Over/Under Voltage Protection
• Battery Chemistry: Lithium-Ion (Li-Ion)
• Voltage - Supply: 8 V ~ 30 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AD7280A
TIMING SPECIFICATIONS
V
Table 3.
Parameter
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
Timing Diagram
CONV
ACQ
ACQ
ACQ
ACQ
DELAY
WAIT
SCLK
QUIET
1
2
3
4
5
6
7
8
9
10
11
12
Sample tested during initial release to ensure compliance. All input signals are specified with t
All timing specifications given are with a 25 pF load capacitance.
Maximum allowed CNVST low pulse time to ensure that a software power-down state is not entered when the CNVST pin is not gated.
Time required for the output to cross 0.4 V or 2.4 V.
t
DD
2
3
10
4
applies when using a continuous SCLK. Guaranteed by design.
= 8 V to 30 V, V
SCLK
SDO
SDI
CS
1
THREE-STATE
Min
425
425
340
340
665
665
1005
1005
1340
1340
5
200
0.4
10
5
4
20
0.45 × t
0.45 × t
100
3
t
3
SS
= 0 V, DV
t
t
2
4
SCLK
SCLK
1
MSB
Typ
560
400
800
1200
1600
200
MSB
CC
= AV
2
MSB – 1
MSB – 1
CC
t
= V
5
3
Max
695
720
465
470
1010
1030
1460
1510
1890
1945
250
1
50
20
28
10
REG
t
6
, V
Figure 2. Serial Interface Timing Diagram
DRIVE
4
= 2.7 V to 5.5 V, T
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
MHz
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
Rev. 0 | Page 6 of 48
t
7
Description
ADC conversion time
−40°C to +85°C
−40°C to +105°C
ADC acquisition time, Bits[D6:D5] of the control register set to 00
−40°C to +85°C
−40°C to +105°C
ADC acquisition time, Bits[D6:D5] of the control register set to 01
−40°C to +85°C
−40°C to +105°C
ADC acquisition time, Bits[D6:D5] of the control register set to 10
−40°C to +85°C
−40°C to +105°C
ADC acquisition time, Bits[D6:D5] of the control register set to 11
−40°C to +85°C
−40°C to +105°C
Propagation delay between the falling edges of CNVST of adjacent
parts in the daisy chain
Time required between the end of conversions and the beginning
of readback of the conversion results
Frequency of serial read clock
Minimum quiet time required between the end of a serial read and
the start of the next conversion
CNVST low pulse
CS falling edge to SCLK rising edge
Delay from CS falling edge until SDO is three-state disabled
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
Data access time after SCLK rising edge
SCLK to data valid hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge
CS rising edge to SDO high impedance
CS high time required between each 32-bit write/read command
A
= −40°C to +105°C, unless otherwise noted.
R
= t
F
= 5 ns (10% to 90% of V
t
8
t
9
32
DRIVE
t
t
11
10
LSB
) and timed from a voltage level of 1.6 V.
LSB
THREE-STATE
t
12