M25P16-VMN6P Micron Technology Inc, M25P16-VMN6P Datasheet - Page 24

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M25P16-VMN6P

Manufacturer Part Number
M25P16-VMN6P
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of M25P16-VMN6P

Cell Type
NOR
Density
16Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC N
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
2M
Supply Current
12mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Compliant

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6.4.4
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SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
S
C
D
Q
sequence
0
High Impedance
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
2
1
0
MSB
7
6
Status Register Out
5
4
3
2
1
0
7
AI02031E

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