P87C52SBBB NXP Semiconductors, P87C52SBBB Datasheet - Page 11
P87C52SBBB
Manufacturer Part Number
P87C52SBBB
Description
MCU 8-Bit 87C 80C51 CISC 8KB EPROM 3.3V/5V 44-Pin PQFP
Manufacturer
NXP Semiconductors
Datasheet
1.P87C52UBAA512.pdf
(38 pages)
Specifications of P87C52SBBB
Package
44PQFP
Device Core
80C51
Family Name
87C
Maximum Speed
33 MHz
Ram Size
256 Byte
Program Memory Size
8 KB
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
EPROM
Number Of Programmable I/os
32
Interface Type
UART
Operating Temperature
0 to 70 °C
Number Of Timers
3
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P87C52SBBB
Manufacturer:
PHILIPS
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672
Part Number:
P87C52SBBB
Manufacturer:
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Company:
Part Number:
P87C52SBBB,557
Manufacturer:
NXP Semiconductors
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Company:
Part Number:
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Manufacturer:
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Philips Semiconductors
2000 Aug 07
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
T2EX Pin
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
T2 Pin
OSC
Position
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
12
Transition
Detector
(MSB)
TF2
C/T2 = 0
C/T2 = 1
Name and Significance
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
Start/stop control for Timer 2. A logic 1 starts the timer.
Timer or counter select. (Timer 2)
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
EXF2
EXEN2
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
Figure 1. Timer/Counter 2 (T2CON) Control Register
Control
RCLK
Figure 2. Timer 2 in Capture Mode
TR2
Control
Capture
TCLK
11
RCAP2L
(8-bits)
EXEN2
TL2
(8-bits)
RCAP2H
TR2
TH2
80C51/87C51/80C52/87C52
C/T2
EXF2
TF2
CP/RL2
(LSB)
Product specification
SU00728
SU00066
Interrupt
Timer 2