SI3233-C-FM Silicon Laboratories Inc, SI3233-C-FM Datasheet
SI3233-C-FM
Specifications of SI3233-C-FM
Related parts for SI3233-C-FM
SI3233-C-FM Summary of contents
Page 1
... CMOS integrated circuit. The integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 V (Si3233M only supply. The ProSLIC controls the phone line through Silicon Labs’ Si3201 Linefeed IC or discrete circuitry. ...
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... Si3233 2 Preliminary Rev. 0.5 ...
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... Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1. Si3230 to Si3233 Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.6. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8. PLL Free-run Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.9. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.10. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability Operation above 125 C junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad Symbol Si3233 DDD DDA1 DDA2 I IN ...
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... Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3233 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used ...
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... Si3233 Table 3. AC Characteristics (Continued 3. 70°C for F-Grade, –40 to 85°C for G-Grade) DDA DDD A Parameter Longitudinal Impedance Longitudinal Current per Pin Notes: 1. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 2. The level of any unwanted tones within the bandwidth kHz does not exceed –55 dBm. ...
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... Indirect Register 23 5 REN load; sine wave 160 Ω –75 V LOOP BAT Programmable in Indirect OS Register 6 Crest factor = 1 Accuracy of ON/OFF Times ↑CAL to ↓CAL Bit At Power Threshold = 300 mW Preliminary Rev. 0.5 Si3233 Min Typ Max Unit Ω 0 — 160 –10 — –4 — Ω ...
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... IH Low Level Input Voltage V IL High Level Output Voltage V OH Low Level Output Voltage V OL Input Leakage Current I L Table 7. Si3233 DC Characteristics 3. 3. 70°C for F-Grade, –40 to 85°C for G-Grade) DDA DDD A Parameter Symbol High Level Input Voltage V IH Low Level Input Voltage ...
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... Forward/reverse OHT, ETBO = 4 mA –70 V BAT I Sleep (RESET = 0) BAT Open (DCOF = 1) Active on-hook Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA LIM Ground-start Ringing PK_RING PK sinewave ringing, REN = BAT BAT Preliminary Rev. 0.5 Si3233 1 2 Max Typ Typ 0.1 0.13 0 110 110 — ...
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... Si3233 Table 9. Switching Characteristics—General Inputs 3. 70°C for F-Grade, –40 to 85°C for G-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are ...
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... SCLK t su1 CS SDI t d1 SDO Figure 2. SPI Timing Diagram t thru su2 Preliminary Rev. 0.5 Si3233 ...
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... All circuit ground should have a single- 15 point connection to the ground plane. 4. Si3201 bottom-side exposed should be electronically and thermally connected to talk ground plane. Figure 3. Si3233/Si3233M Application Circuit Using Si3201 Table 11. Si3233/Si3233M + Si3201 External Component Values Component(s) C1,C2 10 µ Ceramic Low Leakage Electrolytic, ±20% C3,C4 C5,C6 C15,C16,C17,C24 ...
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... Values and configurations for these components can be derived from Table 17 or from App Note 45. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 4. Si3233 DC-DC Converter Circuit Table 12. Si3233 DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20%, low ESR (tan(δ) < 0.08) C10 0.1 µ ...
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... Si3233 SDCH SDCL DCFF DCDRV Figure 5. Si3233M MOSFET/Transformer DC-DC Converter Circuit Table 13. Si3233M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20%, low ESR (tan(δ) < 0.08) C14* C25* 10 µF, Electrolytic, ±20%, low ESR (tan(δ) < 0.08) C27 470 pF, 100 V, X7R, ±20% ...
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... Only one component per system needed. 3. All circuit ground should have a single-point connection to the ground plane. 4. Optional components to improve idle channel noise. Figure 6. Si3233/Si3233M Typical Application Circuit Using Discrete Components Table 14. Si3233/Si3233M External Component Values—Discrete Solution Component(s) 10 µ Ceramic Low Leakage Electrolytic, ±20% C1,C2 220 nF, 100 V, X7R, ± ...
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... Si3233 Table 14. Si3233/Si3233M External Component Values—Discrete Solution (Continued) R15 R21 1/10 W, ±1% (See AN45 or Table 16 for value selection) R28,R29 R32* *Note: Only one component per system needed. VINp TX gain = 0.6622 CMlevel VINm VOUTm VOUTp RX gain = 1.2346 Figure 7. Interface to Broadcom BCM11xx Table 15. External Component Values— ...
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... Table 16. Component Value Selection for Si3233 Component R28 1/ resistor For V DD For V DD R29 1/ resistor For V CLAMP For V CLAMP For V CLAMP Table 17. Component Value Selection Examples for BJT/Inductor DC-DC Converter VDC Maximum Ringing Load/Loop Resistance 3 REN/117 Ω REN/117 Ω REN/117 Ω ...
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... A/D converter. Balanced 5 REN ringing with or without a programmable dc offset is supported. Programmable offset, frequency, waveshape, and cadence allow the Si3233 to ring the widest variety of terminal devices and to reduce external controller requirements. 2.1. Si3230 to Si3233 Differences The hardware and software differences between the ...
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... A “direct” register is one that is mapped directly. 2.2.2. Linefeed Architecture The Si3233 uses either the Si3201 linefeed interface low-cost external circuit to generate the high voltages required for subscriber line interfaces. The ProSLIC uses both voltage and current sensing to control TIP and RING ...
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... Si3233 Table 20. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 Open 001 Forward Active 010 Forward On-Hook Transmission 011 TIP Open 100 Ringing 101 Reverse Active 110 Reverse On-Hook Transmission 111 Ring Open Note: The Linefeed register (LF) is located in direct Register 64. ...
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... W for Q1, 30.4 mW Q2, Q5 0.9 W for Q3 7 0 7.8 W 30.4 mW see equation above see equation above see equation above Bits corre- N/A spond Q6, respectively Preliminary Rev. 0.5 Si3233 4096 ------------------ = 800 τ × P 1.28 MAX ------------------------------ - ----------------- - = = = 42 = 2Ah Resolution 0.0304 Register 21 ...
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... Si3233 Table 22. Associated Power Monitoring and Power Fault Registers (Continued) Power Alarm Interrupt Enable Power Alarm Automatic/Manual Detect *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31) ...
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... It is recommended that a calibration be executed following system power-up. Upon release of the chip reset, the Si3233 will be in the open state. After powering up the dc-dc converter and allowing it to settle for time (t ) the calibration can be initiated. ...
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... T1 specified in Application Note 45 (AN45), and includes several taps on the primary side to facilitate a wide range of input voltages. The Si3233M version of the Si3233 must be used for the application circuit depicted in Figure 5 because the DCFF pin is used to drive M1 directly and therefore must be the same polarity as DCDRV. DCDRV is not used in this circuit option ...
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... RING BAT Range Resolution n/a n/a n/a n 15.564 us 61.035 1.892 us) + 61.035 ns 4 clock cycles 0 to –94 –94 – 1 –13.5 V Preliminary Rev. 0.5 Si3233 Constant V Region R LOOP V TIP RING BAT Register Bit Location DCOF Direct Register 14 DCCAL Direct Register 93 DCN[7:0] ...
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... Si3233 2.3.6. DC-DC Converter During Ringing When the ProSLIC enters the ringing state, it requires voltages well above those used in the active mode. The voltage to be generated and regulated by the dc-dc converter during a ringing burst is set using the VBATH register (direct Register 74). VBATH can be set between 0 and – ...
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... REL bit (direct Register 32, bit 6), which enables reloading of the OSC1, OSC1X, and OSC1Y registers at the expiration of the active timer (OAT1). Preliminary Rev. 0.5 Si3233 phase frequency-shift keying (FSK) 27 ...
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... Si3233 Table 25. Associated Tone Generator Registers Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude Coefficient Oscillator 2 initial phase coefficient Oscillator 2 Active Timer Oscillator 2 Inactive Timer ...
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... Disabled Enabled/ Disabled seconds RAT[15: seconds RIT[15:0] Ringing State = 100b LF[2: –94.5 V VBATH[5: 94.5 V ROFF[15: 100 Hz RCO[15:0] Preliminary Rev. 0.5 Si3233 circuit with programmable the ringing waveform Location Bits Direct Register 34 RVO Direct Register 34 Direct Register 34 Direct Register 34 ROE Direct Register 34 ...
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... Si3233 Table 26. Registers for Ringing Generation (Continued) Ringing amplitude Ringing initial phase Common Mode Bias Adjust During Ringing Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31) ...
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... Loop Current Sense (LCS) value provided by the current monitoring circuitry and reported in direct Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the ringing state as indicated by the Preliminary Rev. 0.5 Si3233 V N AC,PK REN × ...
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... Si3233 Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low pass filter, which removes unwanted ac signal components before threshold detection. The output of the low pass filter is compared to a programmable threshold, RPTP (indirect Register 16). The threshold comparator output feeds a programmable debouncing filter ...
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... NRTP Frequency Hz decimal 16.667 64 20 100 30 112 40 128 50 213 60 256 RPTP hex decimal hex 0200 34 mA 3600 0320 34 mA 3600 0380 34 mA 3600 0400 34 mA 3600 06A8 34 mA 3600 0800 34 mA 3600 Preliminary Rev. 0.5 Si3233 RTDI decimal hex ...
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... PCLK frequency and it can be approximately predicted by the following equation: 2.8. PLL Free-run Operation The Si3233 is capable of operating in the absence of a valid PCLK signal. This feature can be enabled at any time after initialization by setting the PFR bit (register 14, bit 3). When enabled, the Si3233 internally gates off the buffered PCLK signal and applies a reference voltage input to the PLL ...
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... Each device uses the LSB of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered. Preliminary Rev. 0.5 Si3233 35 ...
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... Si3233 SCLK CS SDI SDO SCLK CS SDI SDO High Impedance 36 Don't Care High Impedance Figure 16. Serial Write 8-Bit Mode Don't Care Figure 17. Serial Read 8-Bit Mode Preliminary Rev. 0 Don't Care ...
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... Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select. CS SDO CS SDO CS SDO CS SDO Address Byte R/W Figure 18. SPI Daisy Chain Mode Preliminary Rev. 0.5 Si3233 SDI0 SDI SDITHRU SDI1 SDI SDITHRU SDI2 SDI SDITHRU SDI3 SDI SDITHRU Data Byte ...
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... Si3233 3. Control Registers Indirect registers are accessed through direct registers 28 through 31. Instructions on how to access them is described in “4. Indirect Registers” beginning on page 85. Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 9 Audio Gain Control ...
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... OAT2[15:8] OIT2[7:0] OIT2[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] SLIC LCD[7:0] LFS[2:0] SQH CBY ETBE VOV MNCM MNDIF SPDS VSGN Preliminary Rev. 0.5 Si3233 Bit 3 Bit 2 Bit 1 Bit 0 FSKDAT LF[2:0] ETBO[1:0] ETBA[1:0] FVBAT TRACK AORD AOLD AOPN DBIRAW RTP LCR LCDI[6:0] RTDI[6:0] ILIM[2:0] ...
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... Si3233 Table 29. Direct Register Summary (Continued) Register Name 75 Low Battery Voltage 76 Power Monitor Pointer 77 Line Power Output Monitor 78 Loop Voltage Sense 79 Loop Current Sense 80 TIP Voltage Sense 81 RING Voltage Sense 82 Battery Voltage Sense 1 83 Battery Voltage Sense 2 84 Transistor 1 Current Sense ...
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... Common Mode Balance Calibration Result 107 DC Peak Voltage Calibration Result 108 Enhancement Enable Bit 7 Bit 6 Bit 5 Bit 4 CALMG1[3:0] DACOF[7:0] ILIMEN FSKEN DCSU Preliminary Rev. 0.5 Si3233 Bit 3 Bit 2 Bit 1 Bit 0 CALGC[4:0] CALGIL[3:0] CALMG2[3:0] DACP DACN ADCP ADCN CMBAL[5:0] CMDCPK[3:0] LCVE DCFIL ...
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... Enable SPI daisy chain mode. 6 SPIM SPI Mode Causes SDO to tri-state on rising edge of SCLK of LSB Normal operation; SDO tri-states on rising edge of CS. 5:4 PNI[1:0] Part Number Identification Si3233 01 = Reserved 10 = Reserved 11 = Si3233M 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc PNI[1:0] R Function Preliminary Rev ...
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... Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 ARX[1:0] Analog Receive Path Gain –3 3 Mute Note: ARX affects internally generated audio signals only. Audio received on IGMN/IGMP pins is not impacted Function Preliminary Rev. 0.5 Si3233 ARX[1:0] R/W 43 ...
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... Si3233 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off Reserved 3 TISE Two-Wire Impedance Synthesis Enable Two-wire impedance synthesis disabled Two-wire impedance synthesis enabled. ...
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... DC Bias Power-Off Control Automatic power control Override automatic control and force dc bias circuitry off. 0 SLICOF SLIC Power-Off Control Automatic power control Override automatic control and force SLIC circuitry off. Si3233 DCOF MOF R/W R/W Function Preliminary Rev. 0.5 Si3233 BIASOF SLICOF R/W R/W 45 ...
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... Si3233 Register 15. Power Down Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACM Digital to Analog Converter Manual/Automatic Power Control Automatic power control Manual power control; DACON controls on/off state. 2 DACON Digital to Analog Converter On/Off Power Control. ...
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... Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 O1AP Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending RGAP O2IP O2AP R/W R/W R/W Function Preliminary Rev. 0.5 Si3233 O1IP O1AP R/W R/W R/W 47 ...
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... Si3233 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 6 Q5AP Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. ...
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... INDP Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writ- ing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 Reserved Read returns zero Function Preliminary Rev. 0.5 Si3233 INDP R/W 49 ...
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... Si3233 Register 21. Interrupt Enable 1 Bit D7 D6 Name RGIE Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIE Ringing Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 4 RGAE Ringing Active Timer Interrupt Enable Interrupt masked Interrupt enabled. 3 O2IE Oscillator 2 Inactive Timer Interrupt Enable. ...
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... Power Alarm Q1 Interrupt Enable Interrupt masked Interrupt enabled. 1 LCIE Loop Closure Transition Interrupt Enable Interrupt masked Interrupt enabled. 0 RTIE Ring Trip Interrupt Enable Interrupt masked Interrupt enabled Q3AE Q2AE Q1AE R/W R/W R/W Function Preliminary Rev. 0.5 Si3233 LCIE RTIE R/W R/W R/W 51 ...
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... Si3233 Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 Reserved Read returns zero Function Preliminary Rev. 0 INDE R/W ...
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... IAA at the next indirect register update (16 kHz update rate—a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation IDA[7:0] R/W Function IDA[15:8] R/W Function Preliminary Rev. 0.5 Si3233 ...
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... Si3233 Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate— ...
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... Oscillator 1 Enable Disable oscillator Enable oscillator. 1:0 O1SO[1:0] Oscillator 1 Signal Output Routing Unassigned path (output not connected Assign to transmit path Assign to receive path Assign to both paths OZ1 O1TAE O1TIE R/W R/W R/W Function Preliminary Rev. 0.5 Si3233 O1E O1SO[1:0] R/W R/W 55 ...
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... Si3233 Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. 5 OZ2 Oscillator 2 Zero Cross Enable Signal terminates after active timer expires Signal terminates at zero crossing. ...
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... Ringing Oscillator Enable Ringing oscillator disabled Ringing oscillator enabled. 1 RVO Ringing Voltage Offset offset added to ringing signal offset added to ringing signal. 0 TSWS Trapezoid/Sinusoid Waveshape Select Sinusoid 1 = Trapezoid RTAE RTIE ROE R R/W R/W Function Preliminary Rev. 0.5 Si3233 RVO TSWS R R/W R/W 57 ...
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... Si3233 Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[15:8] Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer— ...
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... OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 µs Register 41. Oscillator 2 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT2[15:8] Oscillator 2 Active Timer OIT1[15:8] R/W Function OAT2[7:0] R/W Function OAT2[15:8] R/W Function Preliminary Rev. 0.5 Si3233 ...
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... Si3233 Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[15:8] Oscillator 2 Inactive Timer. Register 48. Ringing Oscillator Active Timer— ...
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... RIT[7:0] Ringing Inactive Timer. LSB = 125 µs Register 51. Ringing Oscillator Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RIT[15:8] Ringing Inactive Timer RAT[15:8] R/W Function RIT[7:0] R/W Function RIT[15:8] R/W Function Preliminary Rev. 0.5 Si3233 ...
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... Si3233 Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this bit serves as the buffered input for FSK generation bit stream data. ...
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... LF[2:0] Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Function Preliminary Rev. 0.5 Si3233 LF[2:0] R/W 63 ...
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... Si3233 Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. 5 CBY Capacitor Bypass Capacitors CP (C1) and CM (C2) in circuit Capacitors CP (C1) and CM (C2) bypassed. ...
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... Normal operation tracks VBATH register. BAT 2:1 Reserved Read returns zero. 0 TRACK DC-DC Converter Tracking Mode will not decrease below VBATL. BAT tracks V BAT VOV FVBAT R/W R/W Function OV . RING Preliminary Rev. 0.5 Si3233 TRACK R/W , which is defined in indirect Register 41. 65 ...
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... Si3233 Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. 5 MNDIF Differential Mode Manual/Automatic Select. ...
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... LCDI[6:0] Loop Closure Debounce Interval. The value written to this register defines the minimum steady state debounce time. Value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms DBIRAW Function LCDI[6:0] R/W Function Preliminary Rev. 0.5 Si3233 RTP LCR ...
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... Si3233 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12 ...
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... VOC[5:0] R/W Function is positive RING is negative RING VCM[5:0] R/W Function for forward active and forward on-hook trans- TIP for reverse active and reverse on-hook transmission states. RING Preliminary Rev. 0.5 Si3233 –V ). TIP RING –V ). Value may TIP RING ...
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... Si3233 Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = – ...
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... Line Power Output Monitor. This register reports the realtime power output of the transistor selected using PWRMP. The range (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6. The range (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4 Function PWROM[7:0] R Function Preliminary Rev. 0.5 Si3233 PWRMP[2:0] R ...
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... Si3233 Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage ( Positive loop voltage ( Negative loop voltage (V 5:0 LVS[5:0] Loop Voltage Sense Magnitude ...
Page 73
... Reset settings = 0000_0000 Bit Name 7:0 VBATS1[7:0] Battery Voltage Sense 1. This register is one of two registers that reports the realtime voltage ground. The range (0x00) to –95.88 V (0xFF) in .376 V steps VTIP[7:0] R Function VRING[7:0] R Function VBATS1[7:0] R Function Preliminary Rev. 0.5 Si3233 with respect BAT 73 ...
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... Si3233 Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the realtime voltage ground. The range (0x00) to –95.88 V (0xFF) in .376 V steps. Register 84. Transistor 1 Current Sense ...
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... Register 88. Transistor 5 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ5[7:0] Transistor 5 Current Sense. This register reports the realtime current through Q5. The range (0x00) to 80.58 mA (0xFF) in .316 mA steps IQ3[7:0] R Function IQ4[7:0] R Function IQ5[7:0] R Function Preliminary Rev. 0.5 Si3233 ...
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... Si3233 Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the realtime current through Q6. The range (0x00) to 80.58 mA (0xFF) in .316 mA steps. Register 92. DC-DC Converter PWM Period Bit D7 D6 Name ...
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... DC-DC Converter Feed Forward Pin (DCFF) Polarity. This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3233 are offered to support the two relationships DCFF pin polarity is opposite of DCDRV pin (Si3233 DCFF pin polarity is same as DCDRV pin (Si3233M). ...
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... Si3233 Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL CALSP Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system Normal operation or calibration complete Calibration in progress. 5 CALSP Calibration Speedup. ...
Page 79
... Normal operation or calibration complete Calibration enabled or in progress. 0 CALCM Common Mode Balance Calibration. Setting this bit begins calibration of the ac longitudinal balance Normal operation or calibration complete Calibration enabled or in progress CALM1 CALM2 CALDAC R/W R/W R/W Function Preliminary Rev. 0.5 Si3233 CALADC CALCM R/W R/W 79 ...
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... Si3233 Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current. Register 99. TIP Gain Mismatch Calibration Result Bit D7 D6 Name Type ...
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... Register 103. Monitor ADC Offset Calibration Result Bit D7 D6 Name CALMG1[3:0] Type R/W Reset settings = 1000_1000 Bit Name 7:4 CALMG1[3:0] Monitor ADC Offset Calibration Result 1. 3:0 CALMG2[3:0] Monitor ADC Offset Calibration Result CALGC[4:0] R/W Function Function Function Preliminary Rev. 0.5 Si3233 CALGIL[3:0] R CALMG2[3:0] R/W 81 ...
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... Si3233 Register 104. Analog DAC/ADC Offset Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ADCN Negative Analog ADC Offset. Register 105. DAC Offset Calibration Result ...
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... When enabled, this bit invokes a multi-threshold error control algorithm which allows the dc-dc converter to adjust more quickly to voltage changes Normal control algorithm used Multi-threshold error control algorithm used. 4:3 Reserved Read returns zero Function LCVE R/W Function Preliminary Rev. 0.5 Si3233 CMDCPK[3:0] R DCFIL HYSTEN R/W R/W R/W 83 ...
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... Si3233 Bit Name 2 LCVE Voltage-Based Loop Closure. Enables loop closure to be determined by the TIP-to-RING voltage rather than loop cur- rent Loop closure determined by loop current Loop closure determined by TIP-to-RING voltage. 1 DCFIL DC-DC Converter Squelch. When enabled, this bit squelches noise in the audio band from the dc-dc converter con- trol loop ...
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... IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of 16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer. Table 30. Si3230 to Si3233 Indirect Register Cross Reference Si3230 Si3233 ...
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... Si3233 Table 31. Oscillator Indirect Registers Summary (Continued) Addr D15 D14 D13 D12 Table 32. Oscillator Indirect Registers Description Addr 0 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. 1 Oscillator 1 Amplitude Register. Sets tone generator 1 signal amplitude. 2 Oscillator 1 Initial Phase Register. Sets initial phase of tone generator 1 signal. ...
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... This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to –∞ dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. D10 DACG[11:0] ADCG[11:0] Description Preliminary Rev. 0.5 Si3233 ...
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... Si3233 4.3. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes ...
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... REL = 1 (direct Register 32, bit 6). Table 37. FSK Control Indirect Registers Summary Addr D15 D14 D13 D12 Description Voltage (Si3233 only supplied by the dc-dc converter. When the VOV OV should be set between 0 and 9 V (VMIND = 0 to 6h). When the OV D11 D10 FSK0X[15:0] FSK0[15:0] ...
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... Si3233 Table 38. FSK Control Indirect Registers Description Addr 69 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener- ating a space or “0”. When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. ...
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... Pin Descriptions: Si3233 Pin # Name 35 CS Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. 36 INT Interrupt. Maskable interrupt output. Open drain output for wire-ORed operation. 37 PCLK PCM Bus Clock. ...
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... Si3233 Pin # Name 8 CAPP SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. 9 QGND Component Reference Ground. 10 CAPM SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. 11 STIPDC TIP Sense. Analog current input used to sense voltage on the TIP lead. ...
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... Serial Port Data Out. Serial port control data output. 33 SDI Serial Port Data In. Serial port control data input. 34 SCLK Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. Description Preliminary Rev. 0.5 Si3233 93 ...
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... Si3233 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O 13 IRINGN I 14 IRINGP I 15 ITIPN I 16 ITIPP I Bottom-Side — Exposed Pad 94 TIP 1 16 ITIPP ITIPN RING 3 14 ...
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... Add an “R” at the end of the device to denote tape and reel options; 2500 quantity per reel. 3. All devices are lead-free and RoHS-compliant. DCFF Pin Output Package DCDRV QFN-38 DCDRV QFN-38 DCDRV QFN-38 DCDRV QFN-38 n/a SOIC-16 n/a SOIC-16 Preliminary Rev. 0.5 Si3233 Temp Range °C – ° °C – ° °C – °C 95 ...
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... Si3233 8. Package Outline: 38-Pin QFN Figure 19 illustrates the package details for the Si3233. Table 39 lists the values for the dimensions shown in the illustration. Figure 19. 38-Pin Quad Flat No-Lead Package (QFN) Table 39. Package Diagram Dimensions Symbol aaa bbb ccc ddd Notes: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. ...
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... Weight: Approximate device weight is 0.15 grams. Millimeters Symbol Min Max A 1.35 1. 0.15 B .33 .51 C .19 .25 D 9.80 10.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h .25 .50 L .40 1.27 γ — 0.10 θ 0º 8º Preliminary Rev. 0.5 Si3233 x45° h θ L Detail F C See Detail F 97 ...
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... Si3233 OCUMENT HANGE IST Revision 0.1 to Revision 0.5 Updated Section "2.6. Two-Wire Impedance Matching" on page 34 and Register 10, “Two-Wire Impedance Synthesis Control,” on page 44. Removed invalid reference to ZEXT bit. 98 Preliminary Rev. 0.5 ...
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... N : OTES Preliminary Rev. 0.5 Si3233 99 ...
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... Si3233 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...