SI3216M-C-GM Silicon Laboratories Inc, SI3216M-C-GM Datasheet - Page 102

• Manufacturer Part Number: SI3216M-C-GM
• Description: IC SLIC/CODEC 1CH 38QFN
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3216M-C-GM

• Package / Case: *
• Function: Subscriber Line Interface Concept (SLIC), CODEC
• Interface: PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3.13 V ~ 5.25 V
• Current - Supply: 88mA
• Power (watts): 700mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: Audio Tone Generation, BORSCHT Functions, FSK Generation, Ringing and Battery Voltage Generation
• Product: SLIC
• Supply Voltage (min): 3.13 V
• Supply Current: 88 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si3216
Register 108. Enhancement Enable
Reset settings = 0000_0000
102
Name
Type
Bit
7
6
5
4
3
2
Bit
ILIMEN
Reserved
Reserved
ILIMEN
FSKEN
R/W
DCSU
Name
LCVE
D7
FSKEN
R/W
D6
Current Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 99–104). Audio tones are generated using
this new higher frequency, and oscillator 1 active and inactive timers have a finer bit res-
olution of 41.67 µs. This provides greater resolution during FSK caller ID signal genera-
tion.
0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 8 kHz.
DC-DC Converter Control Speedup.
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
Write has no effect.
Read returns zero.
Voltage-Based Loop Closure.
Enables loop closure to be determined by the TIP-to-RING voltage rather than loop cur-
rent.
0 = Loop closure determined by loop current.
1 = Loop closure determined by TIP-to-RING voltage.
DCSU
R/W
D5
D4
Rev. 1.0
D3
Function
LCVE
R/W
D2
DCFIL
R/W
D1
HYSTEN
R/W
D0