SI3211-BT Silicon Laboratories Inc, SI3211-BT Datasheet
SI3211-BT
Specifications of SI3211-BT
Related parts for SI3211-BT
SI3211-BT Summary of contents
Page 1
... It integrates a subscriber line interface circuit (SLIC), voice codec, and battery generation (Si3210) or battery selection (Si3211) into a single CMOS integrated circuit. The battery supply continuously adapts its output voltage to minimize power dissipation and enables the entire circuit to be powered from a single 3 ...
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... Si3210/Si3211 T C ABLE O F ONTENTS 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5. Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2.7. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.8. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.9. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2 ...
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... DDD DDA1 DDA2 IND STG JA Si3201 BAT V INHV STG 3 Rev. 1.5 Si3210/Si3211 Value Unit –0.5 to 6.0 V ±10 mA –0 0.3) V DDD –40 to 100 C –40 to 150 C 70 C/W 35 C/W 0.7 W –0.5 to 6.0 V –104 V (V – 0. 0.3) V BAT DD –0 0. –40 to 100 C – ...
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... Si3210/Si3211 Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3210/11 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. ...
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... Hz to 3.4 kHz at TIP or RING Register selectable ETBO/ETBA Active off-hook 200 Hz to 3.4 kHz Register selectable ETBO/ETBA – Assumes ideal line impedance matching. RING Rev. 1.5 Si3210/Si3211 Typ Max Unit 30 35 — — — dB — — 15 dBrnC — — –75 dBmP — ...
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... Si3210/Si3211 Figure 1. Transmit and Receive Path SNDR Fundamental Output Power (dBm0) Figure 2. Overload Compression Performance 2 Fundamental Input Power (dBm0) Rev. 1.5 Acceptable Region ...
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... Typical Response Figure 3. Transmit Path Frequency Response Rev. 1.5 Si3210/Si3211 Typical Response 7 ...
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... Si3210/Si3211 Figure 4. Receive Path Frequency Response 8 Rev. 1.5 ...
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... Figure 5. Transmit Group Delay Distortion Figure 6. Receive Group Delay Distortion Rev. 1.5 Si3210/Si3211 9 ...
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... Si3210/Si3211 Table 4. Linefeed Characteristics ( 3. 70°C for F-Grade, –40 to 85°C for G-Grade) DDA DDD A Parameter Symbol Loop Resistance Range* R LOOP DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output R Resistance DC Open Circuit Voltage— V OCTO Ground Start DC Output Resistance— ...
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... V DDA DDD Test Condition Min 0 DIO1,DIO2,SDITHRU: I =– DDD SDO, DTX:I = – DOUT – DDD DIO1,DIO2,DOUT,SDITHRU SDO,INT,DTX –10 Rev. 1.5 Si3210/Si3211 Typ Max Unit — 1/2 LSB — 1 LSB — — Typ Max Unit — — V DDD — 0 DDD — — ...
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... Si3210/Si3211 Table 8. Power Supply Characteristics ( 3. °C for F-Grade, – °C for G-Grade) DDA DDD A Parameter Symbol Power Supply Current Analog and Digital I V Supply Current (Si3201 Supply Current BAT V Supply Slew Rate BAT Notes 3.3 V. DDD DDA 5.25 V. DDD DDA 3 ...
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... Conditions t 0.062 c t — — — — — su1 su2 440 cs t 220 cs t — d4 Rev. 1.5 Si3210/Si3211 = 20 pF) L Typ Max Unit — — — Typ Max Unit — — µs — — — — — — — ns — — ns — ...
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... Si3210/Si3211 SCLK t su1 CS SDI t d1 SDO Table 11. Switching Characteristics—PCM Highway Serial Interface V = 3. °C for F-Grade, – °C for G-Grade Parameter PCLK Frequency PCLK Duty Cycle Tolerance PCLK-to-FSYNC Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Delay Time, PCLK Rise to DTX Active ...
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... SVBAT R5 200k C4 R9 220 nF 470 21 SRINGAC 16 SRINGDC R3 200k GND Q9 R21 2N2222 15 VCC 1 1 R29 R28 Note 1 VBAT Rev. 1.5 Si3210/Si3211 VCC L2 47 µH C31 C30 10 µF 10 µF C15 C16 C17 0.1 µF 0.1 µF 0.1 µF 38 SCLK 37 SDI SPI Bus 36 SDO 1 ...
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... Si3210/Si3211 Table 12. Si3210/Si3210M + Si3201 External Component Values Component(s) 10 µ Ceramic Low Leakage C1,C2 Electrolytic, ±20% C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C15,C16,C17,C24 0.1 µ Y5V, ±20% C18,C19 4.7 µF, ceramic X7R, ±20% C26 0.1 µF, 100 V, X7R, ±20% C30,C31 10 µ ...
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... Values and configurations for these components can be derived from “AN45: Design Guide for the Si3210 DC-DC Converter” or Table 21. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 10. Si3210 BJT/Inductor DC-DC Converter Circuit Rev. 1.5 Si3210/Si3211 VDC F1 2 C14 ...
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... Si3210/Si3211 Table 13. Si3210 BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10 0.1 µ X7R, ±20% C14* 0.1 µF, X7R, ±20% C25* 10 µF, Electrolytic, ±20% 200 , 1/10 W, ±5% R16 1/10 W, ±5% (See AN45 or Table 21 for R17 value selection) 1/4 W, ± ...
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... DCDRV NC Notes: 1. Values and configurations for these components can be derived from AN45 or Table 20. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit Rev. 1.5 Si3210/Si3211 VDC C25 C14 1 10 µF 0.1 µF ...
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... Si3210/Si3211 Table 14. Si3210M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C14* 0.1 µF, X7R, ±20% C25* 10 µF, Electrolytic, ±20% C27 470 pF, 100 V, X7R, ±20% R17 200 k, 1/10 W, ±5% 1/4 W, ±5% (See “AN45: Design Guide for R18 the Si3210 DC-DC Converter” or Table 20 for value selection) 1/10 W, ± ...
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... Only one component per system needed. 2. All circuit grounds should have a single- point connection to the ground plane. 3. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. 4. Pin numbers for TSSOP shown. Figure 12. Si3211 Typical Application Circuit Using Si3201 C31 R1 200k 15 STIPDC 20 ...
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... Si3210/Si3211 Table 15. Si3211 + Si3201 External Component Values Component(s) C1,C2 10 µ Ceramic Low-Leakage Electrolytic, ±20% C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C9 0.1 µF, 100 V, X7R, ±20% C15,C16,C17,C24 0.1 µ Y5V, ±20% C18,C19 4.7 µF Ceramic X7R, ±20% C30,C31 10 µ ...
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... C4 R9 220nF 470 21 SRINGAC 16 SRINGDC R3 200k GND R21 Q9 15 2N2222 VCC 1 1 R29 R28 Note 1 VBAT Rev. 1.5 Si3210/Si3211 VCC L2 47 µH C31 C30 10 µF 10 µF C15 C16 C17 0.1 µF 0.1 µF 0.1 µF 38 SCLK 37 SDI SPI Bus 36 SDO 1 CS ...
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... Si3210/Si3211 Table 16. Si3210/Si3210M External Component Values—Discrete Solution Component(s) 10 µ Ceramic Low-Leakage C1,C2 Electrolytic, 20% 220 nF, 100 V, X7R, 20% C3,C4 22 nF, 100 V, X7R, 20% C5,C6 220 nF X7R, 20% C7,C8 0.1 µ Y5V, 20% C15,C16,C17 0.1 µF, 100 V, X7R, 20% C26 C30,C31 10 µ ...
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... The trace resistance between R6 and C26 should equal the trace resistance between R7 and C26. 4. Optional components to improve idle channel noise. 5. Pin numbers for TSSOP shown. VBATL Figure 14. Si3211 Typical Application Circuit Using Discrete Solution R1 200k 15 STIPDC GND 20 STIPAC ...
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... Si3210/Si3211 Table 17. Si3211 External Component Values—Discrete Solution Component(s) 10 µ Ceramic Low Leakage C1,C2 Electrolytic, 20% 220 nF, 100 V, X7R, 20% C3,C4 22 nF, 100 V, X7R, 20% C5,C6 220 nF X7R, 20% C7,C8 0.1 µF, 100 V, X7R, 20% C9 0.1 µ Y5V, 20% C15,C16,C17 C30,C31 10 µ ...
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... Value Package 1210 805 Value Package = 3.3 V: 26.1 k 805 = 5.0 V: 37.4 k 541 k 805 = 85 V: 574 k = 100 V: 676 k Rev. 1.5 Si3210/Si3211 QTDN 5401 R24 RTBN0 3.0k C8 CTBN 100 nF Supplier/Part Number Murata, Johanson, Venkel Comments R28 = ( )/148 µA ...
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... Si3210/Si3211 Table 20. Component Value Selection Examples for Si3210M MOSFET/Transformer DC-DC Converter VDC Maximum Ringing Load/ Loop Resistance 3 REN/117 3 REN/117 5 REN/117 REN/117 Notes: 1. There are other system and software conditions that influence component value selection. Refer to “AN45: Design Guide for the Si3210 DC-DC Converter” for detailed guidance. ...
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... Si3210/Si3211 2.1.1. DC Feed Characteristics The ProSLIC has programmable constant voltage and constant current zones as shown in Figure 16. Open- circuit TIP-to-RING voltage (V voltage zone and is programmable from 94 ...
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... Si3210/Si3211 2.1.2. Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure simplified illustration of the linefeed control loop circuit for TIP or RING and the external components used. ...
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... TIP RING TIP tri-stated, RING active; used for ground start Ringing waveform applied to TIP and RING V > V RING TIP V > audio signal paths powered on RING TIP RING tri-stated, TIP active Rev. 1.5 Si3210/Si3211 Battery Sense DC Emitter Sense BAT V BAT 31 ...
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... Si3210/Si3211 Table 24. Measured Real-Time Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – V TIP RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage Sense BAT Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense ...
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... See equation above. Bits correspond n Q6, respec- tively Bits correspond n Q6, respec- tively 0 = manual mode n enter open state upon power alarm Rev. 1.5 Si3210/Si3211 Register Location* Bits PWRMP[2:0] Direct Register 76 PWROM[7:0] Direct Register 77 PPT12[7:0] Indirect Register 32 PPT34[7:0] Indirect Register 33 PPT56[7:0] Indirect Register 34 ...
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... Si3210/Si3211 LCS Input ISP_OUT Signal LVS Processor LFS LCVE 2.1.6. Loop Closure Transition Detection A loop closure transition event signals that the terminal equipment has gone from on-hook to off-hook or from off- hook to on-hook; detection occurs while the ProSLIC linefeed is in its on-hook transmission or active states. The ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter ...
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... LCR Status (monitor only) Loop Closure Detect LCDI[6:0] Debounce Interval Hysteresis Enable HYSTEN Voltage-Based Loop LCVE Closure Rev. 1.5 Si3210/Si3211 Location Direct Reg. 19 Direct Reg. 22 Indirect Reg. 28 Indirect Reg. 43 Indirect Reg. 35 Direct Reg. 68 Direct Reg. 69 Direct Reg. 108 Direct Reg. 108 ...
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... For higher channel count applications where centralized battery voltage supply is economical or for modular legacy systems where battery voltage is already available, the Si3211 is recommended. 2.2.1. DC-DC Converter General Description (Si3210/Si3210M Only) ...
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... In principle, the regulator output voltage can go as low as |V significant power savings. When TRACK = The RING terminal voltage, however, continues BATL to decrease with decreasing R Rev. 1.5 Si3210/Si3211 Pulse Width register (direct , is offset from the BAT in the active state is BAT ...
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... Si3210/Si3211 The power dissipation on the NPN bipolar transistor driving the RING terminal can become large and may require a higher power rating device. The non-tracking mode of operation is required by specific terminal equipment that, in order to initiate certain data transmission modes, goes briefly on-hook to measure the line voltage to determine whether there is any other off-hook terminal equipment on the same line ...
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... External Battery Switching (Si3211 Only) The Si3211 supports switching between two battery voltages. The circuit for external battery switching is defined in Figure 14. Typically, a high-voltage battery (e.g., – used for on-hook and ringing states, and a low-voltage battery (e.g., – ...
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... Si3210/Si3211 8 kHz Clock OnE Zero 16-Bit Cross OAT Modulo Logic Expire Counter OIT Expire OATn OATnE OITn OITnE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively Figure 20. Simplified Tone Generator Diagram 2.3.2. Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole ...
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... Sets initial phase OSC2Y[15: seconds OAT2[15: seconds OIT2[15:0] Status and control OSS2, OZ2, registers O2TAE, O2TIE, O2E, O2SO[1:0] Rev. 1.5 Si3210/Si3211 frequency-shift keying (FSK) Location Indirect Register 13 Indirect Register 14 Indirect Register 15 Direct Registers 36 & 37 Direct Register 38 & 39 Direct Register 32 Location Indirect Register 16 ...
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... Si3210/Si3211 O1E ... ... 0 AT1 OSS1 Tone Gen. 1 Signal Output Figure 21. Tone Generator Timing Diagram 2.3.4. Enhanced FSK Waveform Generation Silicon revisions C and higher support enhanced FSK generation capabilities, which can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REN = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) and space (0) attributes once during initialization by defining indirect registers 99– ...
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... Indirect Register 19) must be greater than the selected on-hook line voltage setting (VOC, direct Register 72). Using a 70 VPK 20 Hz ringing signal as an example, the equations are as follows: coeff Rev. 1.5 Si3210/Si3211 Register Location Bits TSWS Direct Register 34 RVO Direct Register 34 RTAE ...
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... Si3210/Si3211 15 RCO 0.99211 2 32509 = = 1 70 0.00789 15 ----- - RNGX = -------------------- - 1.99211 RNGY addition, the user must select the sinusoidal ringing waveform by writing TSWS = 0 (direct Register 34, bit 0). 2.4.3. Trapezoidal Ringing In addition to the sinusoidal ringing waveform, the ProSLIC supports trapezoidal ...
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... The recommended values for RPTP, NRTP, and RTDI OVR vary according to the programmed ringing frequency. Register values for various ringing frequencies are given in Table 32. + DBIRAW LPF Debounce – Ring Trip Threshold RPTP Figure 23. Ring Trip Detector Rev. 1.5 Si3210/Si3211 RTP RTIP Interrupt Filter Logic RTDI RTIE 45 ...
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... Si3210/Si3211 Table 31. Associated Registers for Ring Trip Detection Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Detect Debounce Interval Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “ ...
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... DTMF register. If tones occur at the maximum rate of 100 ms per digit, the interrupt must be serviced within that the current digit is not overwritten by a new one. There is no buffering of the digit information. Rev. 1.5 Si3210/Si3211 Location Indirect Register 25 Indirect Register 24 Indirect Register 23 Direct Registers 44 & ...
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... Si3210/Si3211 2.7. Audio Path Unlike traditional SLICs, the codec function is integrated into the ProSLIC. The 16-bit codec offers programmable gain/attenuation blocks and several loopback modes. The signal path block diagram is shown in Figure 25. 2.7.1. Transmit Path In the transmit path, the analog signal fed by the external ac coupling capacitors is amplified by the analog transmit amplifier, ATX, prior to the A/D converter. The gain of the ATX is user-selectable to one of mute/– ...
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... Si3210/Si3211 Rev. 1.5 49 ...
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... Si3210/Si3211 2.7.2. Receive Path In the receive path, the optionally-compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16- bit word. DACG is the receive path programmable gain amplifier, which can be programmed from – ...
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... Power alarm DTMF digit detected Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing active timer expired Ringing inactive timer expired Rev. 1.5 Si3210/Si3211 ). 15 64 PCLK m 51 ...
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... Si3210/Si3211 Pulse metering active timer expired Pulse metering inactive timer expired Indirect register access complete The interface to the interrupt logic consists of six registers. Three interrupt status registers contain one bit for each of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource ...
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... SCLK CS SDI SDO SCLK CS SDI SDO High Impedance Don't Care High Impedance Figure 26. Serial Write 8-Bit Mode Don't Care Figure 27. Serial Read 8-Bit Mode Rev. 1.5 Si3210/Si3211 Don't Care ...
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... Si3210/Si3211 SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select. ...
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... PCLK cycles in a sample period will stop data transmission because TXS or RXS will never equal the PCLK count. Figures 29–32 illustrate the usage of the PCM highway interface to adapt to common PCM standards MSB LSB MSB LSB LSB LSB Rev. 1.5 Si3210/Si3211 HI HI-Z 55 ...
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... Si3210/Si3211 PCLK FSYNC PCLK_CNT 0 1 DRX DTX HI-Z Figure 31. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10) PCLK FSYNC 0 1 PCLK_CNT DRX MSB DTX HI-Z Figure 32. GCI Example, Timeslot 1 (TXS/RXS = 0) 2.13. Companding The ProSLIC supports both µ-255 Law and A-Law companding formats in addition to linear data. These 8-bit companding schemes follow a segmented curve formatted as sign bit, three chord bits, and four step bits. µ ...
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... Value at Segment Endpoints Digital Code 8159 10000000b . . . 4319 4063 10001111b . . . 2143 2015 10011111b . . . 1055 991 10101111b . . . 511 479 10111111b . . . 239 223 11001111b . . . 103 95 11011111b . . . 35 31 11101111b . . . 3 1 11111110b 0 11111111b Rev. 1.5 Si3210/Si3211 1,2 Decode Level 8031 4191 2079 1023 495 231 ...
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... Si3210/Si3211 Table 35. A-Law Encode-Decode Characteristics Segment #intervals X interval size Number 128 Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of all even numbered bits. 58 Value at segment endpoints Digital Code 4096 3968 10101010b . . 2176 ...
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... Interrupt Status 1 19 Interrupt Status 2 20 Interrupt Status 3 21 Interrupt Enable 1 22 Interrupt Enable 2 23 Interrupt Enable 3 24 Decode Status Notes: 1. Si3211 only. 2. Si3210 only. Table 36. Direct Register Summary Bit 7 Bit 6 Bit 5 Bit 4 Setup SPIDC SPIM PNI[1:0] PNI2 PCME PCMF[1:0] TXS[7:0] ...
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... Timer—High Byte 44 Pulse Metering Oscillator Active Timer— Low Byte 45 Pulse Metering Oscillator Active Timer— High Byte 46 Pulse Metering Oscillator Inactive Timer—Low Byte Notes: 1. Si3211 only. 2. Si3210 only. 60 Bit 7 Bit 6 Bit 5 Bit 4 IDA[7:0] IDA[15:8] IAA[7:0] Oscillators OSS1 REL OZ1 ...
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... On-Hook Line Voltage 73 Common Mode Voltage 74 High Battery Voltage 75 Low Battery Voltage 76 Power Monitor Pointer 77 Line Power Output Monitor 78 Loop Voltage Sense Notes: 1. Si3211 only. 2. Si3210 only. Bit 7 Bit 6 Bit 5 Bit 4 PIT[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] SLIC LCD[7:0] LFS[2:0] SQH CBY ...
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... RING Gain Mismatch Calibration Result 99 TIP Gain Mismatch Calibration Result 100 Differential Loop Current Gain Calibration Result 101 Common Mode Loop Current Gain Calibration Result Notes: 1. Si3211 only. 2. Si3210 only. 62 Bit 7 Bit 6 Bit 5 Bit 4 LCSP VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] ...
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... Analog DAC/ADC Offset 105 DAC Offset Calibration Result 106 Common Mode Balance Calibration Result 107 DC Peak Current Calibration Result 108 Enhancement Enable Notes: 1. Si3211 only. 2. Si3210 only. Bit 7 Bit 6 Bit 5 Bit 4 CALMG1[3:0] DACOF[7:0] 2 ILIMEN FSKEN DCSU ZSEXT Rev. 1.5 Si3210/Si3211 Bit 3 ...
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... Enable SPI daisy chain mode. 6 SPIM SPI Mode Causes SDO to tri-state on rising edge of SCLK of LSB Normal operation; SDO tri-states on rising edge of CS. 5:4 PNI[1:0] Part Number Identification Si3210 01 = Si3211 10 = Unused 11 = Si3210M 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc ...
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... GCI GCI Clock Format PCLK per data bit PCLKs per data bit. 0 TRI Tri-state Bit Tri-state bit 0 on positive edge of PCLK Tri-state bit 0 on negative edge of PCLK PCME PCMF[1:0] R/W R/W Function Rev. 1.5 Si3210/Si3211 PCMT GCI TRI R/W R/W R/W 65 ...
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... Si3210/Si3211 Register 2. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data trans- mission begins. See Figure 29 on page 55. ...
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... See Figure 29 on page 55. Register 6. Digital Input/Output Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Function Si3210 Si3211 DOUT DIO2 R/W R/W Rev. 1.5 Si3210/Si3211 RXS[9:8] R DIO1 PD2 PD1 R/W R/W R/W 67 ...
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... DIO2 Pin Input/Output Direction (Si3211 only DIO2 pin is an input DIO2 pin is an output and driven to value of the PD2 bit. Si3210 = Reserved. 2 DIO1 DIO1 Pin Input/Output Direction (Si3211 only DIO1 pin is an input DIO1 pin is an output and driven to value of the PD1 bit. Si3210 = Reserved. 1 PD2 DIO2 Pin Data (Si3211 only) ...
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... Full analog loopback mode enabled. 1 DLM Digital Loopback Mode. (See Figure 25 on page 49 Digital loopback disabled Digital loopback enabled. 0 ALM1 Analog Loopback Mode 1. (See Figure 25 on page 49 Analog loopback disabled Analog loopback enabled Function Rev. 1.5 Si3210/Si3211 ALM2 DLM ALM1 R/W R/W R/W 69 ...
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... Si3210/Si3211 Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHPF HPF bypassed in receive path, RHPF. 6 TXHP Transmit Path High Pass Filter Disable. ...
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... CTR21 (270 + 750 || 150 nF) 101 = Australia/New Zealand #1 (220 + 820 || 120 nF) 110 = Slovakia/Slovenia/South Africa (220 + 820 || 115 nF) 111 = New Zealand #2 (370 + 620 || 310 nF CLC[1:0] TISE R/W R/W Function Rev. 1.5 Si3210/Si3211 TISS[2:0] R/W 71 ...
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... Si3210/Si3211 Register 11. Hybrid Control Bit D7 D6 Name Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = –1.02 dB 101 = –1.94 dB 110 = –2.77 dB 111 = Off 3 Reserved Read returns zero. ...
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... DCOF DC-DC Converter Power-Off Control (Si3210 only Automatic power control Override automatic control and force dc-dc circuitry off. Si3211 = Read returns 1; it cannot be written. 3 MOF Monitor ADC Power-Off Control Automatic power control Override automatic control and force monitor ADC circuitry off. ...
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... Si3210/Si3211 Register 15. Powerdown Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual power control; ADCON controls on/off state. 4 ADCON Analog to Digital Converter On/Off Power Control. ...
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... Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 O1AP Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending RGIP RGAP O2IP R/W R/W R/W Function Rev. 1.5 Si3210/Si3211 O2AP O1IP O1AP R/W R/W R/W 75 ...
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... Si3210/Si3211 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 6 Q5AP Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. ...
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... This bit is set once a pending indirect register service request has been completed. Writ- ing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 DTMFP DTMF Tone Detected Interrupt. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending Function Rev. 1.5 Si3210/Si3211 CMCP INDP DTMFP R/W R/W R/W 77 ...
Page 78
... Si3210/Si3211 Register 21. Interrupt Enable 1 Bit D7 D6 Name PMIE PMAE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIE Pulse Metering Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 6 PMAE Pulse Metering Active Timer Interrupt Enable Interrupt masked Interrupt enabled. 5 RGIE Ringing Inactive Timer Interrupt Enable. ...
Page 79
... Power Alarm Q1 Interrupt Enable Interrupt masked Interrupt enabled. 1 LCIE Loop Closure Transition Interrupt Enable Interrupt masked Interrupt enabled. 0 RTIE Ring Trip Interrupt Enable Interrupt masked Interrupt enabled Q4AE Q3AE Q2AE R/W R/W R/W Function Rev. 1.5 Si3210/Si3211 Q1AE LCIE RTIE R/W R/W R/W 79 ...
Page 80
... Si3210/Si3211 Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 CMCE Common Mode Calibration Error Interrupt Enable Interrupt masked Interrupt enabled. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 DTMFE DTMF Tone Detected Interrupt Enable ...
Page 81
... VAL R Function Rev. 1.5 Si3210/Si3211 DIG[3: ...
Page 82
... Si3210/Si3211 Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate— ...
Page 83
... IAA at the next indirect memory update (a read operation). Register 31. Indirect Address Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 IAS Indirect Access Status indirect memory access pending Indirect memory access pending IAA[7:0] R/W Function Function Rev. 1.5 Si3210/Si3211 IAS R 83 ...
Page 84
... Si3210/Si3211 Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator 1 Automatic Register Reload. This bit should be set for FSK signaling Oscillator 1 will stop signaling after inactive timer expires. ...
Page 85
... O2E Oscillator 2 Enable Disable oscillator Enable oscillator. 1:0 O2SO[1:0] Oscillator 2 Signal Output Routing Unassigned path (output not connected Assign to transmit path Assign to receive path Assign to both paths OZ2 O2TAE O2TIE R/W R/W R/W Function Rev. 1.5 Si3210/Si3211 O2E O2SO[1:0] R/W R/W 85 ...
Page 86
... Si3210/Si3211 Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved Read returns zero. 5 RDAC Ringing Signal DAC/Linefeed Cross Indicator. For ringing signal start and stop, output to TIP and RING is suspended to ensure conti- nuity with dc linefeed voltages ...
Page 87
... Enable oscillator. 1:0 Reserved Read returns zero. Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µ PMAE PMIE R/W R/W Function OAT1[7:0] R/W Function Rev. 1.5 Si3210/Si3211 PMOE R ...
Page 88
... Si3210/Si3211 Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[15:8] Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[7:0] Oscillator 1 Inactive Timer. ...
Page 89
... Name 7:0 OAT2[15:8] Oscillator 2 Active Timer. Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µ OAT2[7:0] R/W Function OAT2[15:8] R/W Function OIT2[7:0] R/W Function Rev. 1.5 Si3210/Si3211 ...
Page 90
... Si3210/Si3211 Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[15:8] Oscillator 2 Inactive Timer. Register 44. Pulse Metering Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PAT[7:0] Pulse Metering Active Timer. ...
Page 91
... PIT[15:8] Pulse Metering Inactive Timer. Register 48. Ringing Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[7:0] Ringing Active Timer. LSB = 125 µ PIT[7:0] R/W Function PIT[15:8] R/W Function RAT[7:0] R/W Function Rev. 1.5 Si3210/Si3211 ...
Page 92
... Si3210/Si3211 Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RIT[7:0] Ringing Inactive Timer. ...
Page 93
... Loop Closure Debounce Interval for Automatic Ringing. This register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. The value may be set between 0 ms (0x00) and 159 ms (0x7F) in 1.25 ms steps Function LCD[7:0] Function Rev. 1.5 Si3210/Si3211 FSKDAT R ...
Page 94
... Si3210/Si3211 Register 64. Linefeed Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real-time linefeed state. Automatic operations may cause actual linefeed state to deviate from the state defined by linefeed register (e.g., when linefeed equals ringing state, LFS will equal on-hook transmission state during ringing silent period and ringing state during ring burst) ...
Page 95
... External Transistor Bias Levels—Active Off-Hook State. DC bias current which flows through external BJTs in the active off-hook state. Increasing this value increases the compliance of the ac longitudinal balance circuit Reserved CBY ETBE ETBO[1:0] R/W R/W R/W Function Rev. 1.5 Si3210/Si3211 ETBA[1:0] R/W 95 ...
Page 96
... FVBAT V Manual Setting (Si3210 only). BAT 0 = Normal operation tracks V BAT Si3211 = Read returns 0; it cannot be written. 2 Reserved Si3210 = Read returns zero. Si3211 = Read returns one. 1 BATSL Battery Feed Select (Si3211 only). This bit selects between high and low battery supplies Low battery selected (DCSW pin low). ...
Page 97
... SPDS Speed-Up Mode Enable Speed-up disabled Automatic speed-up. 3 ABAT Battery Feed Automatic/Manual Select (Si3211 only Automatic mode disabled Automatic mode enabled (automatic switching to low battery in off-hook state). 2 AORD Automatic/Manual Ring Trip Detect Manual mode Enter off-hook active state automatically upon ring trip detect. ...
Page 98
... Si3210/Si3211 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0100 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the real-time output of ring trip and loop closure detect circuits before debouncing ...
Page 99
... Name 7:3 Reserved Read returns zero. 2:0 ILIM[2:0] Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 20 mA (0x00) and 41 mA (0x07 steps RTDI[6:0] R/W Function Function Rev. 1.5 Si3210/Si3211 ILIM[2:0] R/W 99 ...
Page 100
... Si3210/Si3211 Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity ( –V TIP –V TIP 5:0 VOC[5:0] On-Hook Line Voltage ...
Page 101
... Si3211 typical application circuit drawings, Figure VBATL[5:0] R/W Function . The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V must be set equal to the voltage supplied BATL node shown in the Si3211 typical application circuit drawings, Figure 12 on Rev. 1.5 Si3210/Si3211 must be greater than or BATH D2 D1 ...
Page 102
... Si3210/Si3211 Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the selected transistor is read in the PWROM register. ...
Page 103
... Negative loop current (reverse direction). 5:0 LCS[5:0] Loop Current Sense Magnitude. This register reports the magnitude of the loop current. The range 78. 1.25 mA steps LVS[5:0] R Function > TIP RING < TIP RING LCS[5:0] R Function Rev. 1.5 Si3210/Si3211 – TIP RING –V ). The TIP RING 103 ...
Page 104
... Si3210/Si3211 Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real-time voltage at TIP with respect to ground. The range (0x00) to –95.88 V (0xFF) in .376 V steps. Register 81. RING Voltage Sense Bit ...
Page 105
... Transistor 2 Current Sense. This register reports the real-time current through Q2. The range (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current VBATS2[7:0] R Function IQ1[7:0] R Function IQ2[7:0] R Function Rev. 1.5 Si3210/Si3211 with respect BAT 105 ...
Page 106
... Si3210/Si3211 Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the real-time current through Q3. The range (0x00) to 9.59 mA (0xFF) in 37.6 µA steps. Register 87. Transistor 4 Current Sense Bit D7 D6 Name ...
Page 107
... This bit sets the PWM period for the dc-dc converter. The range is 3.906 µs (0x40) to 15.564 µs (0xFF) in 61.035 ns steps. Si3211 = Reserved. Bit 6 is fixed to one and read-only, so there are two ranges of operation: 3.906 µs–7.751 µs, used for MOSFET transistor switching. ...
Page 108
... DCFF pin polarity is opposite of DCDRV pin (Si3210 DCFF pin polarity is same as DCDRV pin (Si3210M). Si3211 = Reserved. 4:0 DCTOF[4:0] DC-DC Converter Minimum Off Time (Si3210 only). This register sets the minimum off time for the pulse width modulated dc-dc converter control. T Si3211 = Reserved. 108 Si3210 DCPOL R ...
Page 109
... Bit D7 D6 Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width (Si3210 only). Pulse width of DCDRV is given (DCPW – DCTOF – 4) Si3211 = Reserved. Si3210 DCPW[7:0] R Si3211 Function Rev. 1.5 Si3210/Si3211 ...
Page 110
... Si3210/Si3211 Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins calibration of the entire system Normal operation or calibration complete Calibration in progress. 5 CALSP Calibration Speedup. ...
Page 111
... Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current CALM1 CALM2 R/W R/W Function CALGMR[4:0] Function Rev. 1.5 Si3210/Si3211 CALDAC CALADC CALCM R/W R/W R R/W 111 ...
Page 112
... Si3210/Si3211 Register 99. TIP Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMT[4:0] Gain Mismatch of IE Tracking Loop for TIP Current. Register 100. Differential Loop Current Gain Calibration Result Bit D7 D6 ...
Page 113
... Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ADCN Negative Analog ADC Offset Function Function DACP R/W Function Rev. 1.5 Si3210/Si3211 CALGIL[3:0] R CALMG2[3:0] R DACN ADCP ADCN R/W R/W R/W 113 ...
Page 114
... Si3210/Si3211 Register 105. DAC Offset Calibration Result Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DACOF[7:0] DAC Offset Calibration Result. Register 106. Common Mode Balance Calibration Result Bit D7 D6 Name Type Reset settings = 0010_0000 Bit Name 7:6 Reserved Read returns zero. ...
Page 115
... When enabled, this bit invokes a multi-threshold error control algorithm which allows the dc-dc converter to adjust more quickly to voltage changes Normal control algorithm used Multi-threshold error control algorithm used. Si3210 DCSU ZSEXT R/W R/W Si3211 ZSEXT SWDB R/W R/W Function Rev. 1.5 Si3210/Si3211 LCVE DCFIL HYSTEN R/W R/W R LCVE HYSTEN R/W R/W 115 ...
Page 116
... Internal resistor used to generate 600 + 2.1 µF and 900 + 2.16 µF impedances Internal resistor removed from circuit. 3 SWDB Battery Switch Debounce (Si3211 only). When enabled, this bit allows debouncing of the battery switching circuit only when tran- sitioning from debounce used debounce period used. ...
Page 117
... Note: The values of all indirect registers are undefined following the reset state. Table 37. DTMF Indirect Registers Summary Addr. D15 D14 D13 D12 D11 D10 ROW0[15:0] ROW1[15:0] ROW2[15:0] ROW3[15:0] COL[15:0] FWDTW[15:0] REVTW[15:0] ROWREL[15:0] COLREL[15:0] ROW2[15:0] COL2[15:0] PWRMIN[15:0] HOTL[15:0] Rev. 1.5 Si3210/Si3211 117 ...
Page 118
... Si3210/Si3211 Table 38. DTMF Indirect Registers Description Addr. 0 DTMF Row 0 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of power in row 0 to total power in the row band is greater than ROW0, a row 0 signal is detected. ...
Page 119
... Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but must be written to zeroes. Table 39. Oscillator Indirect Registers Summary Addr. D15 D14 D13 D12 D11 ROFF[5: D10 OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OSC2[15:0] OSC2X[15:0] OSC2Y[15:0] RCO[15:0] RNGX[15:0] RNGY[15:0] PLSD[15:0] PLSX[15:0] PLSCO[15:0] Rev. 1.5 Si3210/Si3211 119 ...
Page 120
... Si3210/Si3211 Table 40. Oscillator Indirect Registers Description Addr. Oscillator 1 Frequency Coefficient. 13 Sets tone generator 1 frequency. Oscillator 1 Amplitude Register. 14 Sets tone generator 1 signal amplitude. Oscillator 1 Initial Phase Register. 15 Sets initial phase of tone generator 1 signal. Oscillator 2 Frequency Coefficient. 16 Sets tone generator 2 frequency. Oscillator 2 Amplitude Register. ...
Page 121
... This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. D11 D10 DACG[11:0] ADCG[11:0] Description Rev. 1.5 Si3210/Si3211 Reference Page 48 48 121 ...
Page 122
... Si3210/Si3211 4.4. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but must be written to zeroes ...
Page 123
... This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of direct Register 108. The range is 0– 1.27 mA steps. Description , to be supplied by the dc-dc converter. OV should be set between 0 and should be set between 0 and 13 Rev. 1.5 Si3210/Si3211 Reference Page ...
Page 124
... Si3210/Si3211 4.5. FSK Control For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6). Table 45. FSK Control Indirect Registers Summary Addr ...
Page 125
... PCM bus. May be short or long pulse format. Reset. Active low input. Hardware reset used to place all control registers in the default state. DC Monitor/General Purpose I/O. DC-DC converter monitor input used to detect overcurrent situations in the converter (Si3210 only). General purpose I/O (Si3211 only). Rev. 1.5 Si3210/Si3211 TSSOP ...
Page 126
... Description DC Monitor/General Purpose I/O. DC-DC converter monitor input used to detect overcurrent situations in the converter (Si3210 only). General purpose I/O (Si3211 only). Analog Supply Voltage. Analog power supply for internal analog circuitry. Current Reference. Connects to an external resistor used to provide a high accuracy reference current ...
Page 127
... DCFF/DOUT DC Feed-Forward/High Current General Purpose Output. Feed-forward drive of external bipolar transistors to improve dc-dc converter efficiency (Si3210 only). High current output pin (Si3211 only DCDRV/DCSW DC Drive/Battery Switch. DC-DC converter control signal output which drives external bipolar transistor (Si3210 only). Battery switch control signal output which drives external bipolar transistor (Si3211 only) ...
Page 128
... Si3210/Si3211 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O 13 IRINGN I 14 IRINGP I 15 ITIPN I 16 ITIPP I Bottom-Side — Exposed Pad 128 TIP 1 16 ITIPP ITIPN RING ...
Page 129
... TSSOP-38 n/a TSSOP-38 n/a TSSOP-38 n/a QFN-38 n/a QFN-38 n/a SOIC-16 n/a SOIC-16 Rev. 1.5 Si3210/Si3211 Lead-Free Temperature and RoHS- Compliant Yes °C Yes – °C Yes °C Yes – °C Yes °C Yes – °C Yes ° ...
Page 130
... Eval Board, Daughter Card Si3210-QFN Eval Board, Daughter Card Si3210-TSSOP Eval Board, Daughter Card Si3210-TSSOP Eval Board, Daughter Card Si3210M-TSSOP Eval Board, Daughter Card Si3210M-TSSOP Eval Board, Daughter Card Si3211-TSSOP Eval Board, Daughter Card Rev. 1.5 Linefeed Interface Discrete Si3201 Discrete Si3201 Discrete Si3201 ...
Page 131
... Figure 33 illustrates the package details for the Si321x. Table 48 lists the values for the dimensions shown in the illustration aaa E (L) Figure 33. 38-Pin Quad Flat No-Lead Package (QFN) 2X bbb C B ccc D 38X L C SEATING PLANE Detail A Detail B Pin-1 Identifier 38 1 (b) Option 1 Chamfered Corner Rev. 1.5 Si3210/Si3211 D2 DETAIL "B" 38X b ddd DETAIL "A" Option 2 Corner Square 131 ...
Page 132
... Si3210/Si3211 Table 48. Package Diagram Dimensions Symbol aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1982. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 132 1,2,3 Millimeters ...
Page 133
... PCB Land Pattern: 38-Pin QFN Figure 34 shows the recommended land pattern for the Si3210/11 QFN-38 package. Table 49 lists the values for the dimensions shown in the illustration. Figure 34. QFN-38 Land Pattern Drawing Si3210/Si3211 Rev. 1.5 133 ...
Page 134
... Si3210/Si3211 Table 49. QFN-38 PCB Land Pattern Dimensions Dimension C1 Pad column spacing C2 Pad row spacing E X1 Pin pad width X2 Thermal pad width Y1 Pin pad width Y2 Thermal pad length Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. ...
Page 135
... Max — — 1.20 0.05 — 0.15 0.80 1.00 1.05 0.17 — 0.27 0.09 — 0.20 9.60 9.70 9.80 6.40 BSC 4.30 4.40 4.50 0.50 BSC 0.45 0.60 0.75 0.25 BSC 0° — 8° 0.10 0.08 0.20 Rev. 1.5 Si3210/Si3211 135 ...
Page 136
... Si3210/Si3211 8.2.2. PCB Land Pattern: 38-Pin TSSOP Figure 36 illustrates the recommended land pattern for the Si3210/11 TSSOP-38 package. Table 51 lists the values for the dimensions shown in the illustration. Figure 36. TSSOP-38 PCB Land Pattern Drawing Table 51. PCB Land Pattern Dimensions Dimension Notes: 1 ...
Page 137
... Min A — A1 0.00 A2 1.25 b 0.31 c 0.17 D 9.90 BSC D1 3.45 E 6.00 BSC E1 3.90 BSC E2 2.20 e 1.27 BSC L 0.40 L2 0.25 BSC h 0.25 0° 0.10 0.20 0.10 0.25 Rev. 1.5 Si3210/Si3211 Max 1.75 0.15 — 0.51 0.25 3.65 2.40 1.27 0.50 8° 137 ...
Page 138
... Si3210/Si3211 8.3.2. PCB Land Pattern: 16-Pin ESOIC Figure 38 illustrates the recommended land pattern for the Si3201 SOIC-16 package. Table 53 lists the values for the dimensions shown in the illustration. Figure 38. SOIC-16 PCB Land Pattern Drawing Table 53. SOIC-16 PCB Land Pattern Dimensions Dimension ...
Page 139
... Ordering Part Number and that the product revision level is st indicated by the first (1 ) character of the Manufacturing Code. Si3210/Si3211 Pack ing format, e.g., tape-and-reel Pack age and temperature range Revision level (if applicable Part variant (if applicable) ...
Page 140
... Si3210/Si3211 10. Package Marking (Top Mark) 10.1. QFN Package Table 54. Explanation of QFN Top Mark Line 1 Marking: Silicon Labs prefix Device number Device variant (optional) Separator Package/temperature range Line 2 Marking: YY=Year WW=Work Week TTTTTT=Mfg Code Line 3 Marking: Circle=0.5 mm Diameter Lower Left-Justified Circle=1.3 mm Diameter ...
Page 141
... RFAIXX=Mfg Code Line 3 Marking: Circle=0.5 mm Diameter Lower Left-Justified Circle=1.3 mm Diameter Center-Justified Country of Origin ISO Code Abbreviation Si3210/Si3211 “Si” e.g., “3210” e.g., “M” “–” e.g., “FM’, “GM”, etc Date of manufacture Internal manufacturing code; 1st character=product revision level Pin 1 Identifier “ ...
Page 142
... Si3210/Si3211 10.3. SOIC (Si3201) Package Table 56. Explanation of SOIC Top Mark Silicon Labs prefix Device number Line 1 Marking: Separator Package/temperature range Circle=0.5 mm Diameter Center-Justified Circle=1.3 mm Diameter Lower Left-Justified Line 2 Marking: YY=Year WW=Work Week TTTTTT 142 Figure 41. SOIC Top Mark Diagram “Si” ...
Page 143
... Compliant” Figure , “,” on page 16. Added additional decoupling components to VDDA1, VDDA2, and VDDD. Figure 12, “Si3211 Typical Application Circuit Using Si3201,” on page 21. Added additional decoupling components to VDDA1, VDDA2, and VDDD. Figure 13, “Si3210/Si3210M Typical Application Circuit Using Discrete Components,” ...
Page 144
... Updated "8.3.1. Package Outline: 16-Pin ESOIC" on page 137 with more detailed package drawing. Revision 1.44 to Revision 1.45 Added Si3211-E-FT and Si3211-E-GT to Ordering Guide Clarified Ordering Guide Replaced "X" with revision letter "E" in all ordering ...
Page 145
... N : OTES Si3210/Si3211 Rev. 1.5 145 ...
Page 146
... Si3210/Si3211 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...