DS21554LBN+ Maxim Integrated Products, DS21554LBN+ Datasheet - Page 74

• Manufacturer Part Number: DS21554LBN+
• Description: IC TXRX E1 5V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21554LBN+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 75mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

HSR: HDLC STATUS REGISTER (Address = B1 Hex)
Note: The RPE, RPS, and TMEND bits are latched and are cleared when read.
SYMBOL
TMEND
(MSB)
RHALF
THALF
FRCL
FRCL
RNE
RPE
RPS
TNF
POSITION
RPE
HSR.7
HSR.6
HSR.5
HSR.4
HSR.3
HSR.2
HSR.1
HSR.0
Framer Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1)
consecutive zeros have been detected at RPOSI and RNEGI.
Receive Packet End. Set when the HDLC controller detects either the
finish of a valid message (i.e., CRC check complete) or when the
controller has experienced a message fault such as a CRC checking error,
or an overrun condition, or an abort has been seen. The setting of this bit
prompts the user to read the RHIR register for details.
Receive Packet Start. Set when the HDLC controller detects an opening
byte. The setting of this bit prompts the user to read the RHIR register for
details.
Receive FIFO Half Full. Set when the receive 64-byte FIFO fills beyond
the halfway point. The setting of this bit prompts the user to read the
RHIR register for details.
Receive FIFO Not Empty. Set when the receive 64-byte FIFO has at
least one byte available for a read. The setting of this bit prompts the user
to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64-byte FIFO
empties beyond the halfway point. The setting of this bit prompts the user
to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64-byte FIFO has at
least one byte available. The setting of this bit prompts the user to read the
THIR register for details.
Transmit Message End. Set when the transmit HDLC controller has
finished sending a message. The setting of this bit prompts the user to read
the THIR register for details.
RPS
RHALF
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NAME AND DESCRIPTION
RNE
THALF
TNF
TMEND
(LSB)