CY8C5248LTI-030 Cypress Semiconductor Corp, CY8C5248LTI-030 Datasheet - Page 49

• Manufacturer Part Number: CY8C5248LTI-030
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5248LTI-030

• Lead Free Status / Rohs Status: Compliant

8.7.1 Current DAC
The IDAC can be configured for the ranges 0 to 32 µA, 0 to 256
µA, and 0 to 2.04 mA. The IDAC can be configured to source or
sink current.
8.7.2 Voltage DAC
For the VDAC, the current DAC output is routed through
resistors. The two ranges available for the VDAC are 0 to
1.024 V and 0 to 4.096 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
9. Programming, Debug Interfaces,
The Cortex-M3 has internal debugging components, tightly
integrated with the CPU, providing the following features:
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
SWD supports all programming and debug features of the
device. The SWV provides trace output from the DWT and ITM.
For more information on PSoC 5 programming, refer to the
application note
PSoC
Cortex-M3 debug and trace functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
Document Number: 001-66236 Rev. *A
SWD access
FPB block for implementing breakpoints and code patches
DWT block for implementing watchpoints, trigger resources,
and system profiling
ITM for support of printf-style debugging
Resources
®
5.
AN64359 - In-System Programming for
Reference
Source
PRELIMINARY
Figure 8-6. DAC Block Diagram
Scaler
with the PSoC Creator IDE. PSoC interfaces are fully compatible
with industry standard third party tools.
All Cortex-M3 debug and trace modules are disabled by default
and can only be enabled in firmware. If not enabled, the only way
to reenable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables them. Disabling debug and trace features, robust flash
protection, and hiding custom analog and digital functionality
inside the PSoC device provide a level of security not possible
with multichip application solutions. Additionally, all device
interfaces can be permanently disabled (Device Security) for
applications concerned about phishing attacks due to a
maliciously reprogrammed device. Permanently disabling
interfaces is not recommended in most applications because the
designer then cannot access the device. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
9.1 Debug Port Acquisition
Prior to programming or debugging, the debug port must be
acquired. There is a time window after reset within which the Port
Acquire must be completed. This window is initially 8 µs; if eight
clocks are detected on the SWDCK line within the 8 µs period,
the time window will then be extended to 400 µs to complete the
port acquire operation. The port acquire key must be transmitted
over one of the two SWD pin pairs; see
49. For a detailed description of the acquire key sequence, refer
to the Technical Reference Manual.
9.2 SWD Interface
SWD uses two pins, either two port 1 pins or the USBIO D+ and
D- pins. The USBIO pins are useful for in system programming
of USB solutions that would otherwise require a separate
programming connector. One pin is used for the data clock and
the other is used for data input and output. SWD can be enabled
on only one of the pin pairs at a time. SWD is used for debugging
or for programming the flash memory. In addition, the SWD
interface supports the SWV trace output. The SWD interface
also includes the SWV interface, see
page 51. When using the SWD/SWV pins as standard GPIO,
make sure that the GPIO functionality and PCB circuits do not
interfere with SWD/SWV use. The SWV trace output is
automatically activated whenever the SWD is activated.
PSoC
I
I
1x , 8x , 64x
1x , 8x , 64x
source
sink
Range
Range
3R
R
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5: CY8C52 Family Datasheet
Vout
Iout
“SWV Interface”
SWD Interface
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