EFM32TG110F32-QFN24 Energy Micro, EFM32TG110F32-QFN24 Datasheet - Page 7

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EFM32TG110F32-QFN24

Manufacturer Part Number
EFM32TG110F32-QFN24
Description
MCU 32-Bit EFM32 ARM Cortex M3 RISC 32KB Flash 2.5V/3.3V 24-Pin QFN EP
Manufacturer
Energy Micro
Datasheet

Specifications of EFM32TG110F32-QFN24

Package
24QFN EP
Device Core
ARM Cortex M3
Family Name
EFM32
Maximum Speed
32 MHz
Ram Size
4
Program Memory Size
32
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
32 Bit
Program Memory Type
Flash
Number Of Programmable I/os
17
Interface Type
I2C/I2S/SPI/UART/USART
On-chip Adc
2-chx12-bit
On-chip Dac
1-chx12-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
3

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2.2 Configuration Summary
2.3 Memory Map
2011-07-26 - d0013_Rev0.92
The features of the EFM32TG110 is a subset of the feature set described in the EFM32TG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
The EFM32TG110 memory map is shown in Figure 2.2 (p. 8) , with RAM and Flash sizes for the
largest memory configuration.
Module
Cortex-M3
DBG
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
I2C0
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
DAC0
OPAMP
AES
GPIO
Configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
IrDA
I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Not all pins available
Full configuration
17 pins
...the world's most energy friendly microcontrollers
7
Pin Connections
NA
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
NA
NA
NA
NA
CMU_OUT0, CMU_OUT1
NA
NA
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0]
TIM1_CC[2:0]
NA
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[1:0], ACMP0_O
ACMP1_CH[1:0], ACMP1_O
NA
ADC0_CH[7:6]
DAC0_OUT[0], DAC0_OUTxALT
Outputs: OPAMP_OUT0,
OPAMP_OUT0ALT,
OPAMP_OUT1ALT, Inputs:
OPAMP_P1, OPAMP_N1
NA
Available pins are shown in
Table 4.3 (p. 48)
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