MAX3107EAG+ Maxim Integrated Products, MAX3107EAG+ Datasheet - Page 28

• Manufacturer Part Number: MAX3107EAG+
• Description: IC UART SPI/I2C 128 FIFO 24SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107EAG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.71 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI/I
and Internal Oscillator
Bit 0: RTimeout
The RTimeout bit indicates that stale data is present in the receive FIFO. RTimeout is set when the youngest character
resides in the RxFIFO for longer than the period programmed into the RxTimeOut register. The timeout counter restarts
when at least one character is read out of the RxFIFO or a new character is received by the RxFIFO. If the value in
RxTimeOut is zero, RTimeout is disabled. RTimeout is cleared when a word is read out of the RxFIFO or a new word is
received. The RTimeout flag can generate an ISR[0] interrupt, if enabled through LSRIntEn[0].
SpclChrIntEn—Special Character Interrupt Enable Register
Bits 7 and 6: No Function
Bit 5: MltDrpIntEn
The MltDrpIntEn bit enables routing the SpclCharInt[5]: MultiDropInt interrupt to ISR[1]. If MltDrpIntEn is set low
(default), the MultiDropInt is not routed to the ISR[1].
Bit 4: BREAKIntEn
The BREAKIntEn bit enables routing the SpclCharInt[4]: BREAKInt interrupt to ISR[1]. If BREAKIntEn is set low (default),
the BREAKInt is not routed to the ISR[1].
Bit 3: XOFF2IntE
The XOFF2IntEn bit enables routing the SpclCharInt[3]: XOFF2Int interrupt to ISR[1]. If XOFF2IntEn is set low (default),
the XOFF2Int is not routed to the ISR[1].
Bit 2: XOFF1IntEn
The XOFF1IntEn bit enables routing the SpclCharInt[2]: XOFF1Int interrupt to ISR[1]. If XOFF1IntEn is set low (default),
the XOFF1Int is not routed to the ISR[1].
Bit 1: XON2IntEn
The XON2IntEn bit enables routing the SpclCharInt[1]: XON2Int interrupt to ISR[1]. If XON2IntEn is set low (default),
the XON2Int is not routed to the ISR[1].
Bit 0: XON1IntEn
The XON1IntEn bit enables routing the SpclCharInt[0]: XON1Int interrupt to ISR[1]. If XON1IntEn is set low (default),
the XON1Int is not routed to the ISR[1].
28
ADDRESS:
MODE:
RESET
NAME
_____________________________________________________________________________________
BIT
2
C UART with 128-Word FIFOs
—
7
0
0x05
R/W
—
6
0
MltDrpIntEn
5
0
BREAKIntEn
4
0
XOFF2IntEn
3
0
XOFF1IntEn
2
0
XON2IntEn
1
0
XON1IntEn
0
0