AGLN125V2-VQG100 Actel, AGLN125V2-VQG100 Datasheet - Page 57

• Manufacturer Part Number: AGLN125V2-VQG100
• Manufacturer: Actel

Figure 2-15 • Output Register Timing Diagram
Table 2-66 • Output Data Register Propagation Delays
Data_out
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
Preset
DOUT
Clear
CLK
For specific junction temperature and voltage supply levels, refer to
values.
Output Register
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
1.5 V DC Core Voltage
50%
1
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
J
50%
= 70°C, Worst-Case V
50%
A dv a n c e v 0. 3
50%
t
Description
OWPRE
t
OPRE2Q
50%
50%
t
t
ORECPRE
50%
OCLR2Q
50%
t
OWCLR
CC
50%
50%
= 1.425 V
50%
IGLOO nano DC and Switching Characteristics
t
ORECCLR
Table 2-6 on page 2-6
50%
t
OCKMPWH
t
50%
OREMPRE
t
50%
OCKMPWL
0.00
0.24
0.00
0.24
0.19
0.31
0.28
Std.
1.00
0.51
1.34
1.34
0.00
0.19
for derating
t
OREMCLR
50%
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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