LTC6994CS6-2#PBF Linear Technology, LTC6994CS6-2#PBF Datasheet - Page 18

• Manufacturer Part Number: LTC6994CS6-2#PBF
• Manufacturer: Linear Technology

Specifications of LTC6994CS6-2#PBF

• Lead Free Status / Rohs Status: Compliant

LTC6994-1/LTC6994-2
applicaTions inForMaTion
Settling Time
Following a 2× or 0.5× step change in I
put delay takes approximately six master clock cycles
(6 • t
An example is shown in Figure 12, using the circuit in
Figure 10.
Coupling Error
The current sourced by the SET pin is used to bias the
internal master oscillator. The LTC6994 responds to
changes in I
lent settling time. However, this fast response also makes
the SET pin sensitive to coupling from digital signals, such
as the IN input.
18
2µs/DIV
MASTER
2V/DIV
5V/DIV
5V/DIV
DELAY
V
CTRL
OUT
IN
LTC6994-1
V
DIVCODE = 0
R
R
t
OUT
+
SET
SET
MOD
= 3.3V
) to settle to within 1% of the final value.
= 3µs AND 6µs
= 200k
Figure 12. Typical Settling Time
= 464k
almost immediately, which provides excel-
20µs/DIV
699412 F12
SET
, the out-
Even an excellent layout will allow some coupling between
IN and SET. Additional error is included in the specified
accuracy for N
that ÷1 supply variation is dependent on coupling from
rising or falling inputs.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
IN (or any other fast-edge, wide-swing signal).
–0.2
–0.4
–0.6
–0.8
–1.0
1.0
0.8
0.6
0.4
0.2
Figure 13. Delay Drift vs Supply Voltage
0
2
DIV
RISING EDGE DELAY
R
N
SET
DIV
= 1
= 1 to account for this. Figure 13 shows
= 50k
FALLING EDGE DELAY
3
SUPPLY (V)
4
5
699412 F13
6
699412fa