L9929 STMicroelectronics, L9929 Datasheet
L9929
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L9929 Summary of contents
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... DIAGNOSTIC BY SPI OR STATUS-FLAG ■ (CONFIGURABLE) ENABLE AND DISABLE INPUT ■ SO20 POWER PACKAGE ■ 2 Description The L9929 is an SPI controlled H-Bridge, de- signed for the control of DC and stepper motors in safety critical applications and under extreme en- vironmental conditions. Figure 2. Block Diagram IN1 IN2 DI EN ...
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... L9929 Table 2. Pin Function N° Pin 1 GND Ground 2 SCK/SF SPI-Clock/Status-flag 3 IN1 Input Supply voltage Supply voltage S 6 OU1 Output 1 7 OU1 Output serial out 9 SI serial in 10 GND Ground 11 GND Ground 12 DMS Diagnostic-Mode selection (+ Supply Voltage for SPI-Interface Enable 14 OU2 Output 2 ...
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... Device used in SPI mode kHz 20kHz Min. Typ. Max -0.5 -0.5 Min. Typ. Max. -40 +150 +175 -55 +125 -40 +125 160 175 190 150 165 180 Min. Typ. Max. 4 (*) 4.4 4.7 200 2.5 2.8 3 L9929 Unit Unit °C °C °C °C 3 °C/W °C °C Unit 3/21 ...
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... L9929 Table 5. Electrical Characteristcs (continued -40 to +150° 28V Symbol Parameter Logic inputs V Logic Input Voltage High IH IN1, IN2, DI Logic Input Voltage Low IL IN1, IN2, DI Logic Input Voltage Hysteresis H IN1, IN2, DI Logic Input Current I IN1, IN2 Logic Input Current Detection Time EN, DI ...
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... DI 50 ddis OUT n 10% D01AT473 90 Reaching Switch-off LOAD CURRENT current, limitation phase is started by triggering CURRENT LIMITATION PHASE DETAIL typ. 8. SWITCH_OFF TIME IN CURRENT LIMITATION CURRENT LIMITATION BLANKING TIME b t doff 10% D01AT472 Z 90% t D01AT474 r OVERCURRENT OVERCURRENT DETECTION t b L9929 5/21 ...
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... Table 5. Electrical Characteristics (continued) Spi Interface The timing of L9929 is defined as follows: - The change at output (SO) is forced by the rising edge of the SCK signal. - The input signal (SI) is taken over on the falling edge of the SCK signal active without any clocks at SCK is not allowed - The data received during a writing access is taken over into the internal registers on the rising edge of the SS signal, if exactly 16 SPI clocks have been counted during SS = active ...
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... SIL V High Level SIH ∆ V Hysteresis SI C Input Capacity SI -I Input Current SI Output SO (Tristate output of the L9929 (SPI output); On active reset (DI) output tristate.) V Low Level SOL V High Level SOH C Capacity SO -I Leakage Current SO Input DMS (Supply-Input for the SPI-Inteface and Selection Pin for SPI- or SF-Mode) ...
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... L9929 Table 5. Electrical Characteristcs (continued) Symbol Parameter t Transfer Delay (8) dt (referred to master) t Serial clock high time (9) SCKH (referred to master) t Access time (10) SCKL (referred to master) Clock inactive before chipselect becomes valid (11) Clock inactive after chipselect becomes valid (12) t Rise-, fall time rs TIMING Diagnostic Threshold (Open Load Detection DMS > ...
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... Free wheeling is finshed, if the voltage-level on OUn is positive again. 2. statical g.) all output-stages switched off. Figure 10 GND I LOAD V OUn are reset via DI or EN. I >10.6 A OUT1,2 T >175° <4.5V (at least down to 2.5V) Vs-GND CURRENT FREE WHEELING CARRYNG - S S Zº S HIGH IMPEDANCE Z D01AT478 L9929 9/21 ...
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... L9929 always operates in slave mode whereas the controller provides the master function. The maximum baud rate is 2 MBaud (200pF). Applying an active slave select signal at SS L9929 is selected by the SPI master the data input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master. ...
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... SO remains high impedant for the complete frame regardless which frametype is applied. 5) Check byte: Simultaneously to the receipt of an SPI instruction L9929 transmitts a check byte via the out- put SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial bitpattern and a flag indicating an invalid instruction of the previous access. ...
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... In addition any access is invalid if the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses (-> See Note). 5.4 SPI Communication Figure 12. Reading access / 8 bit 5.5 SPI Instruction The uppermost 2 bit of the instruction byte contains the chipadress. The chipaddress of L9929 is 00. MSB INSTR5 SPI Instruction bit 7,6 CPAD1,0 ...
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... Diagnosis-Bit2 of OUT1 Diagnosis-Bit1 of OUT2 Diagnosis-Bit2 of OUT2 Is set to „0“ in case of current limitation Is set to „0“ in case of temperature dependet current limitation Is set to „0“ in case of overtemperature Shows the wired-or state of the Pins EN and TRANS_F Description 2 1 DIA20 Dia11 Description L9929 0 0 DIA10 13/21 ...
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... L9929 Encoding of the Diagnostic Bits of the Output-Stages OUT1 and OUT2 DIA21 DIA20 - - - - - - - - Description of DIA_REG Bit7 EN 5.8 Device Identifier and Revision Number The IC's identifier is used for production test purposes and features plug & play functionality depending on the systems software release made device-number and a revision number each one read-only acces- sible via standardised instructions ...
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... Figure 14. Application example with Status-Flag VOLTAGE V BATT REGULATOR POWER-ON RESET DMS IN1 V IN2 CC DI SCK µC RESET I.E. WATCH DOG µP DMS 47K IN1 IN2 µC DI RESET I.E. WATCH DOG µP UB OUT1 M OUT2 GND D01AT481 UB OUT1 M OUT2 GND D01AT482 L9929 15/21 ...
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... L9929 Figure 15. Application examples for Overvoltage- and Reverse-Voltage Protection Version 1 REVERSE POLARITY PROTECTION VIA MAIN RELAIS H-BRIDGE Version 2 REVERSE POLARITY PROTECTION VIA ACTIVE DIODE H-BRIDGE D01AT483 6 ESD-SOLIDITY The connection pins of the IC have to be protected against Electrostatic Discharge ESD) by suitable integrated protection structures. ...
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... OUT1 OUT2 VBatt int 5V 1.5 mA OUT2 OUT1 detected on normal operation 0 SC detected on normal operation 1 SC detected on normal operation 1 SC detected on normal operation 0 OL not detected Double Fault 0 OL detected 0 OL detected 1 OL not detected Double Fault IN2 L9929 17/21 ...
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... L9929 8 APPENDIX B Figure 18. Voltage Supply of SPI-Logic and EN/DI-Logic EN EN/DI- Logic DI DMS SO SI SPI- Logic SCK SS 18/21 VBatt Output- Stage internal Vcc DMS = GND EN/DI-Logic is supplied from internal VCC DMS = VCC EN/DI-Logic is supplied from DMS (OR int. VCC) Status EN/DI Undervoltage on VBatt Failure and Status ...
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... A e DETAIL BOTTOM VIEW PSO20MEC OUTLINE AND MECHANICAL DATA JEDEC MO-166 PowerSO20 DETAIL A lead slug a3 DETAIL B 0.35 Gage Plane - SEATING PLANE (COPLANARITY 0056635 I L9929 19/21 ...
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... L9929 10 Revision History Table 7. Revision History Date Revision 07-Mar-2005 20/21 1 First Issue Description of Changes ...
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