MC14519BCL Motorola, MC14519BCL Datasheet

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MC14519BCL

Manufacturer Part Number
MC14519BCL
Description
Quad exclusive NOR gate
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage 1.1 GHz
PLL Frequency Synthesizer
Includes On–Board 64/65 Prescaler
interface capable of direct usage up to 1.1 GHz. A special architecture makes
this PLL very easy to program because a byte–oriented format is utilized. Due
to the patented BitGrabber
random access of the three registers. Thus, tuning can be accomplished via a
3–byte serial transfer to the 24–bit A register. The interface is both SPI and
MICROWIRE
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
powered from 2.7 to 5.5 V. This is optimized for 3.0 V systems. The
phase/frequency detector A PD out output must be powered from 4.5 to 5.5 V,
and is optimized for a 5 volt supply.
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
the three counters (R, A, and N) simultaneously.
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 3
1/98
MOTOROLA
The MC145192 is a low–voltage single–package synthesizer with serial
The device features a single–ended current source/sink phase detector A
The MC145192 phase/frequency detector B R and V outputs can be
This part includes a differential RF input which may be operated in a
In order to have consistent lock times and prevent erroneous data from being
The double–buffered R register allows new divide ratios to be presented to
Motorola, Inc. 1998
Maximum Operating Frequency: 1100 MHz @ V in = 200 mV p–p
Operating Supply Current: 6 mA Nominal at 2.7 V
Operating Supply Voltage Range (V DD and V CC Pins): 2.7 to 5.0 V
Operating Supply Voltage Range of Phase Frequency Detector A
(V PD Pin) = 4.5 to 5.5 V
Operating Supply Voltage Range of Phase Detector B (V PD Pin) = 2.7 to 5.5 V
Current Source/Sink Phase Detector Output Capability: 2 mA Maximum
Gain of Current Source/Sink Phase/Frequency Detector Controllable via Serial Port
Operating Temperature Range: – 40 to 85 C
R Counter Division Range: (1 and) 5 to 8191
N Counter Division Range: 5 to 4095
A Counter Division Range: 0 to 63
Dual–Modulus Capability Provides Total Division up to 262,143
High–Speed Serial Interface: 2 Megabits per Second
Output A Pin, When Configured as Data Out, Permits Cascading of Devices
Two General–Purpose Digital Outputs — Output A: Totem–Pole (Push–Pull) with Four Output Modes
Power–Saving Standby Feature with Patented Orderly Recovery for Minimizing Lock Times,
Standby Current: 30 A
Evaluation Kit Available (Part Number MC145192EVK)
See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
TN98012200
compatible.
registers, no address/steering bits are required for
Output B: Open–Drain
20
20
ORDERING INFORMATION
REF out
TEST 1
MC145192F
MC145192DT
PD out
MC145192
GND
V PD
LD
Rx
1
f in
R
V
PIN ASSIGNMENT
1
1
2
3
4
5
6
7
8
9
10
SOG Package
TSSOP
Order this document
20
19
18
17
16
15
14
13
12
11
SOG PACKAGE
CASE 948D
CASE 751J
DT SUFFIX
by MC145192/D
F SUFFIX
REF in
DATA IN
CLOCK
ENABLE
OUTPUT A
OUTPUT B
V DD
TEST 2
V CC
f in
TSSOP
MC145192
1

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MC14519BCL Summary of contents

Page 1

... Standby Current Evaluation Kit Available (Part Number MC145192EVK) See Application Note AN1253/D for Low–Pass Filter Design, and AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp. REV 3 1/98 TN98012200 MOTOROLA Motorola, Inc ...

Page 2

... OUTPUT B (OPEN–DRAIN OUTPUT) 13 TEST 2 9 TEST 1 This device contains protection circuitry to guard against damage due to high static volt- ages or electric fields. However, precautions must be taken to avoid applications of any volt- age higher than maximum rated voltages to this high–impedance circuit. MOTOROLA ...

Page 3

... I T Total Operating Supply Current ( Pins) * The nominal values are 2.7 V and 2 5.0 V and 5.5 V These are not guaranteed limits. MOTOROLA Phase/Frequency Detector 2.7 to 5.5 V with V DD Test Condition Device in Reference Mode, DC Coupled Device in Reference Mode, DC Coupled 2 5 out = 20 A, Device in Reference Mode I out = – ...

Page 4

... MC145192 Test Condition V out = 0 out = 0 out variation 20% Parameter Parameter Guaranteed Limit V PD Unit 4 5 5.5 12 4.5 0.5 to 4.0 V 5.5 0 Guaranteed Limit Unit dc to 2.0 MHz 200 ns 200 ns 200 ns 200 Guaranteed Limit Unit 50 ns 100 ns * cycles 250 ns 100 s MOTOROLA ...

Page 5

... OUTPUT A 50% (DATA OUT) 10% t TLH t THL Figure 1. VALID 50% DATA 50% CLOCK Figure 3. TEST POINT DEVICE UNDER TEST * Includes all probe and fixture capacitance. Figure 5. Test Circuit MOTOROLA SWITCHING WAVEFORMS V DD 50% ENABLE GND OUTPUT A OUTPUT ENABLE 50% GND GND CLOCK 50% FIRST CLOCK DEVICE UNDER TEST * Includes all probe and fixture capacitance ...

Page 6

... MHz 2 3 MHz dc 5 MHz dc 1 MHz 20 140 ns — — 0.01 F TEST REF in OUTPUT A POINT ( DEVICE UNDER V in TEST * 50 TEST REF out POINT V CC GND REF out 50% TEST POINT Includes all probe and fixture capacitance. Figure 12. Test Circuit MOTOROLA ...

Page 7

... SOG PACKAGE Marker Figure 13. Normalized Input Impedance — Series Format (R + jX) MOTOROLA 4 Capacitive Frequency Resistance Reactance (MHz 100 574 – 881 500 57.9 – 242 800 38.3 – 148 1100 31.6 – 103 (100 MHz to 1100 MHz Capacitance (pF) 1 ...

Page 8

... See Fig- ure 17. The maximum frequency at which the phase detec- tors operate is 1 MHz. Therefore, the frequency should not exceed 1 MHz. If A23 = high and A22 = low, Output A is configured This signal is the buffered output of the 12–stage N counter. NOTE NOTE MOTOROLA ...

Page 9

... Figure 7. Note that driven while f in must be tied to ground via a capacitor. Motorola does not recommend driving f in while terminating f in because this configuration is not tested for sensitivity. The sensitivity is dependent on the frequency as shown in the Loop Specifications table. ...

Page 10

... R and V (Pins 3 and 4) Double–Ended Phase/Frequency Detector Outputs. These outputs can be combined externally to generate a loop error signal. Through use of a Motorola patented tech- nique, the detector’s dead zone has been eliminated. There- fore, the phase/frequency detector is characterized by a linear transfer function. The operation of the phase/fre- quency detector is described below and is shown in Fig- ure 19 ...

Page 11

... Nominal MC145192 PD out Source Current vs Rx Resistance NOTE: The MC145192 is optimized for Rx values in the range. For example, to achieve 0 output current preferable to use a 30–k resistor for Rx and bit settings for 25% (as shown in Table 3). MOTOROLA For optimum performance should be bypassed to GND using a low–inductance capacitor mounted very close to these pins ...

Page 12

... Table 2. PD out Current Low with Output A NOT Selected as “Port”; Also, Default Mode When Output A Selected as “Port” out Current MC145192 Table 3. PD out Current High with Output A NOT C3 0 70% 0 80% 1 90% 1 100 LSB C0 Selected as “Port” out Current 0 25% 1 50% 0 75% 1 100% MOTOROLA ...

Page 13

... Figure 16. A Register Access and Format (24 Clock Cycles are Used) MOTOROLA MC145192 13 ...

Page 14

... Figure 17. R Register Access and Format (16 Clock Cycles Are Used) MC145192 R10 NOT ALLOWED COUNTER = NOT ALLOWED NOT ALLOWED NOT ALLOWED COUNTER = COUNTER = COUNTER = COUNTER = · · · · · · · · · · · · COUNTER = COUNTER = HEXADECIMAL VALUE NOTE NOTE LSB (NOTE 8190 8191 MOTOROLA ...

Page 15

... NOTE: The PD out either sources or sinks current during out–of–lock conditions. When locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the low pass filter capacitor. PD out , R , and V are shown with the polarity bit (POL) = low; see Figure 15 for POL. Figure 19. Phase/Frequency Detectors and Lock Detector Output Waveforms MOTOROLA 100 ns MINIMUM 5 1 ...

Page 16

... CRYSTAL OSCILLATOR CONSIDERATIONS The following options may be considered to provide a ref- erence frequency to Motorola’s CMOS frequency synthe- sizers. USE OF A HYBRID CRYSTAL OSCILLATOR Commercially available temperature–compensated crystal oscillators (TCXOs) or crystal–controlled data clock oscilla- tors provide very stable reference frequencies. An oscillator capable of CMOS logic levels at the output may be direct or dc coupled to REF in ...

Page 17

... D. Kemper, L. Rosine, “Quartz Crystals for Frequency Table 4. Partial List of Crystal Manufacturers Motorola — Internet Address http://motorola.com NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers. MOTOROLA Control”, Electro–Technology , June 1969. ...

Page 18

... AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970. AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design, 1987. AN1253/D, An Improved PLL Design Method Without n and , Motorola Semiconductor Products, Inc., 1995. MC145192 18 ...

Page 19

... The R counter is programmed for a divide value = REF Typically the tuning resolution required for the VCO. Also, the VCO frequency divided this determines the values (N, A) that must be programmed into the N and A counters, respectively. DATA IN CMOS MCU NOTE: See related Figures 25, 26, and 27. MOTOROLA 20 1 REF out REF ...

Page 20

... MOTOROLA ...

Page 21

... Figure 26. Accessing the A Registers of Two Cascaded Devices MOTOROLA Ç Ç Ç Ç * Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 22

... MOTOROLA ...

Page 23

... 0.13 (0.005 TSSOP (THIN SHRUNK SMALL OUTLINE PACKAGE PIN 1 IDENTIFICATION 1 C 0.100 (0.004 -T- SEATING PLANE SECTION A-A MOTOROLA PACKAGE DIMENSIONS F SUFFIX CASE 751J–02 - 0.10 (0.004) M -T- SEATING PLANE S DT SUFFIX CASE 948D–03 K 20X REF 0.200 (0.004 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14 ...

Page 24

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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