MC74HC534AN Motorola, MC74HC534AN Datasheet

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MC74HC534AN

Manufacturer Part Number
MC74HC534AN
Description
Octal 3-stage inverting D flip-flop
Manufacturer
Motorola
Datasheet
Octal 3-State
Inverting D Flip-Flop
High–Performance Silicon–Gate CMOS
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
with the rising edge of the Clock. The Output Enable input does not affect the
states of the flip–flops, but when Output Enable is high, the outputs are
forced to the high impedance state. Thus, data may be stored even when the
outputs are not enabled.
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
outputs.
3/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
The MC54/74HC534A is identical in pinout to the LS534. The device
Data meeting the setup time is clocked, in inverted form, to the outputs
The HC534A is identical in function to the HC564 which has the data
This device is similar in function to the HC374A, which has noninverting
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 282 FETs or 68.5 Equivalent Gates
OUTPUT ENABLE
INPUTS
DATA
CLOCK
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
11
1
LOGIC DIAGRAM
3–1
12
15
16
19
2
5
6
9
PIN 20 = V CC
PIN 10 = GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
INVERTING
OUTPUTS
REV 7
MC54/74HC534A
20
20
X = Don’t Care
Z = High Impedance
Output
Enable
20
OUTPUT
1
ENABLE
1
H
L
L
L
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
ORDERING INFORMATION
GND
1
Q1
Q0
D1
Q2
Q3
D0
D2
D3
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Clock
L,H,
1
2
3
4
5
6
7
8
9
10
X
CERAMIC PACKAGE
PLASTIC PACKAGE
D
H
L
X
X
SOIC PACKAGE
20
19
18
17
16
15
14
13
12
11
CASE 751D–04
CASE 732–03
CASE 738–03
DW SUFFIX
N SUFFIX
J SUFFIX
Ceramic
Plastic
SOIC
No Change
V CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK
Output
Q
H
L
Z

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MC74HC534AN Summary of contents

Page 1

... In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 282 FETs or 68.5 Equivalent Gates LOGIC DIAGRAM DATA D3 13 INPUTS CLOCK 1 OUTPUT ENABLE 3/97 Motorola, Inc. 1997 INVERTING 12 OUTPUTS PIN PIN 10 = GND 3–1 REV 7 MC54/74HC534A J SUFFIX CERAMIC PACKAGE 20 CASE 732–03 ...

Page 2

... Plastic DIP: – from 125 _ C Ceramic DIP: – from 100 _ to 125 _ C SOIC Package: – from 125 _ C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...

Page 3

... NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– ...

Page 4

... Q 10% t TLH t THL Figure 1. CLOCK MOTOROLA Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 5

... High–Speed CMOS Logic Data DL129 — Rev 6 TEST CIRCUITS OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance EXPANDED LOGIC DIAGRAM 3–5 MC54/74HC534A TEST POINT CONNECT WHEN 1 k TESTING t PLZ AND t PZL CONNECT TO GND WHEN TESTING t PHZ AND t PZH Figure MOTOROLA ...

Page 6

... SEATING PLANE –A– –T– SEATING PLANE –A– –B– 20X 0.010 (0.25 18X K MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 732–03 ISSUE SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE 0.25 (0.010 0.25 (0.010 SUFFIX PLASTIC SOIC PACKAGE CASE 751D– ...

Page 7

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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