SAA7196H Philips Semiconductors, SAA7196H Datasheet
SAA7196H
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DATA SHEET SAA7196 Digital video decoder, Scaler and Clock generator circuit (DESCPro) Product specification File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1996 Nov 04 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 Decoder part 7.1.1 Chrominance processor 7.1.2 Luminance processor 7.1.3 Synchronization 7.2 Expansion port (see Fig.2) 7 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 1 FEATURES Digital 8-bit luminance input [video (Y) or CVBS] Digital 8-bit chrominance input [CVBS or C from CVBS, Y/C, S-Video (S-VHS or Hi8)] Luminance and chrominance signal processing for main standards PAL, NTSC and SECAM ...
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... O f input clock frequency BCK T operating ambient temperature amb 4 ORDERING INFORMATION TYPE NUMBER NAME SAA7196H QFP120 1996 Nov 04 2 C-bus interface is The programming of the subaddresses for the scaler part becomes effective at the first Vertical Sync (VS) pulse after a transmission. PARAMETER PACKAGE DESCRIPTION plastic quad fl ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 5 BLOCK DIAGRAM 1996 Nov 04 5 Product specification SAA7196 pagewidth full handbook, ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 1996 Nov 04 6 Product specification SAA7196 pagewidth full handbook, ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 6 PINNING SYMBOL PIN STATUS XTAL 1 XTALI 2 SDA 3 SCL CSA 5 CHR0 6 CHR1 7 CHR2 8 CHR3 9 CHR4 10 CHR5 11 CHR6 12 CHR7 DDD1 CTST SSD1 CVBS0 17 CVBS1 18 CVBS2 19 CVBS3 20 CVBS4 21 CVBS5 22 CVBS6 23 CVBS7 24 HSY 25 HCL ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SYMBOL PIN STATUS CREFB 39 LLC 40 LLCB 41 LLC2 42 BTST 43 RTCO DDD3 VMUX SSD3 SODD 48 SVS 49 SHREF 50 PXQ 51 LNQ 52 VOE 53 HFL 54 INCADR 55 VCLK 56 VRO31 57 VRO30 58 VRO29 SSD4 V 61 DDD4 VRO28 62 VRO27 63 VRO26 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SYMBOL PIN STATUS VRO19 71 VRO18 72 VRO17 73 VRO16 SSD5 i. DDD5 VRO15 78 VRO14 79 VRO13 80 VRO12 81 VRO11 82 VRO10 83 VRO9 84 VRO8 85 VRO7 86 VRO6 87 VRO5 88 VRO4 89 VRO3 DDD6 VRO2 92 VRO1 93 VRO0 94 DIR 95 YUV15 96 YUV14 97 YUV13 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SYMBOL PIN STATUS YUV2 112 YUV1 113 YUV0 114 HREF 115 VS 116 HS 117 AP 118 SP 119 V 120 SSD7 1996 Nov 04 I/O digital 16-bit video input/output signal (bit 2); colour difference signals (UV) I/O digital 16-bit video input/output signal (bit 1) ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth XTAL 1 XTALI 2 SDA 3 SCL CSA 5 CHR0 6 CHR1 7 CHR2 8 CHR3 9 10 CHR4 CHR5 11 CHR6 12 CHR7 13 V DDD1 14 CTST 15 V SSD1 16 CVBS0 17 CVBS1 18 CVBS2 19 CVBS3 20 CVBS4 21 CVBS5 22 CVBS6 23 CVBS7 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 7 FUNCTIONAL DESCRIPTION 7.1 Decoder part PAL, NTSC and SECAM standard colour signals based on line-locked clock are decoded (see Fig.27). In Y/C mode, digitized luminance CVBS7 to CVBS0 and chrominance CHR7 to CHR0 signals (digitized in two external ADCs) are input ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Mode 3: YUV15 to YUV0 and HREF/VS terminals are inputs. External YUV15 to YUV0 is input to the scaler with HREF/VS reference from external. LLCB/CREFB clock system of the SAA7196 is used. handbook, full pagewidth digital signal value All levels are related to EBU colour bar ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 7.3 Monitor controls BCS 7.3.1 B RIGHTNESS AND CONTRAST CONTROLS The luminance signal can be controlled via I (see Table 16) by the bits BRIG7 to BRIG0 and CONT6 to CONT0. Table 1 Brightness control BRIGHTNESS CONTROL ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 5 YUV-bus format on expansion port; note 1 PIN n YUV15 Ye7 YUV14 Ye6 YUV13 Ye5 YUV12 Ye4 YUV11 Ye3 YUV10 Ye2 YUV9 Ye1 YUV8 Ye0 YUV7 Ue7 YUV6 Ue6 YUV5 Ue5 YUV4 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth LLCB CREFB HREF DIR UV dec (from decoder) UV ext (from external port scaler t = 1.5LLC + t from 3-state(min) PZ(min) t > t from 3-state to 3-state t = 1.5LLC + t to 3-state(max) PZ(max) Fig.5 Real-time switching between mode 0 and mode 1 (internal/external YUV15 to YUV0). ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 625 1 handbook, full pagewidth input CVBS HREF VS ODD (RTSO) 313 handbook, full pagewidth input CVBS HREF VS ODD (RTSO) 1996 Nov 1st field. 314 315 316 317 b. 2nd field Fig.6 VS and ODD timing on expansion port (50 Hz). ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 525 1 handbook, full pagewidth input CVBS HREF VS ODD (RTSO) 263 handbook, full pagewidth input CVBS HREF VS ODD (RTSO) 1996 Nov 1st field. 264 265 266 267 b. 2nd field. Fig.7 VS and ODD timing on expansion port (60 Hz). ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth CVBS HSY (1) 191 HSY programming range (step size: 2/LLC) HCL (1) 127 HCL programming range (step size: 2/LLC) processing delay CVBS - YUV Y output HREF (50 Hz) PLIN (RTS1) (50 Hz only) ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) LLCB CREFB HREF Byte numbers for pixels: Y signal and V signal Y signal and V signal LLCB CREFB HREF Byte numbers for pixels: 762 Y signal and V signal U762 634 Y signal and V signal U634 Fig ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth digital signal value 254 white 100% 235 128 luminance levels black signal range. Fig.10 Input and output signal levels on expansion port. 7.3.3 RTCO 44 OUTPUT PIN This real-time control and status output signal contains serial information about actual system clock, subcarrier frequency and PAL/SECAM sequence (see Fig ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth H/L transition (counter start) 128 clock cycles RTCO (1) Sequence bit: SECAM: 0 equals DB-line; 1 equals DR-line. PAL: 0 equals (R Y) line normal; 1 equals (R NTSC: 0 (no change). (2) Reserve bits: 276 for 50 Hz systems; 188 for 60 Hz systems. ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 7.4.1 D ECIMATION FILTERS The decimation filters perform accurate horizontal filtering of the input data stream. The signal bandwidth is matched in front of the pixel decimation stage, thus disturbing artifacts, caused by the pixel dropping, are reduced. ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 7.4.5.1 Vertical bypass region Data are not scaled and independent of I FS0; the output format is always 8-bit gray scale (monochrome). The SAA7196 outputs all active pixels of a line, defined by the HREF input signal if the vertical bypass region is active ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 7.4.6 O UTPUT DATA REPRESENTATION AND LEVELS Output data representation of the YUV data can be modified by bit MCT (subaddress 30). The DC gain is 1 for YUV input data. The corresponding RGB levels are defined by the matrix equations; they are limited to the range 254 in the 8-bit domain according to CCIR 601 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) It means: HFL = 1 at the rising edge of INCADR: the ‘end of line’ is reached; request for line address increment HFL = 0 at the rising edge of INCADR: the ‘end of field/frame’ is reached; request for line and pixel address reset ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 8 VRAM port output data formats for bits (continued in Table 9) EFE-bit = 0 and VOF-bit = 1 (controllable via I FS1 = 0; FS0 = 0 RGB 5-5-5+ PIXEL 32-BIT WORDS OUTPUT BIT VRO31 VRO30 R4 R4 VRO29 R3 R3 VRO28 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 9 VRAM port output data formats for bits (continued from Table 8) EFE-bit = 0 and VOF-bit = 1 (controllable via I FS1 = 0; FS0 = 0 RGB 5-5-5+ PIXEL 32-BIT WORDS OUTPUT BIT VRO15 VRO14 R4 R4 VRO13 R3 R3 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 10 VRAM port output data formats for bits (continued in Table 11) EFE-bit = 1 and VOF-bit = 1 (controllable via I FS1 = 0; FS0 = 0 (1) RGB 5-5-5+ PIXEL 16-BIT WORDS OUTPUT BIT VRO31 VRO30 R4 R4 VRO29 R3 R3 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 11 VRAM port output data formats for bits (continued from Table 10) EFE-bit = 1 and VOF-bit = 1 (controllable via I FS1 = 0; FS0 = 0 RGB 5-5-5+ PIXEL 16-BIT WORDS OUTPUT BIT VRO15 X X VRO14 X X VRO13 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 12 VRAM port output formats for bits (continued in Table 13) EFE-bit = 0 and VOF-bit = 0 (controllable via I FS1 = 0; FS0 = 0 RGB 5-5-5+ PIXEL 16-BIT LONG WORD OUTPUT BIT VRO31 Z VRO30 R4 Z VRO29 R3 Z VRO28 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 13 VRAM port output data formats for bits (continued from Table 12) EFE-bit = 0 and VOF-bit = 0 (controllable via I FS1 = 0; FS0 = 0 RGB 5-5-5+ PIXEL 16-BIT LONG WORD OUTPUT BIT VRO15 Z VRO14 Z R4 VRO13 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) PIXCLK handbook, full pagewidth 1/2LLC FIFO memory 7 filling level HFL VCLK VOE VRO(n) (1) Minimum 8 words available in FIFO. (2) Maximum 32LLC (16PIXCLK). (3) 1 transfer cycle (8 VCLK cycles). Fig.13 Output port transfer to VRAM at 32-bit data format without scaling. If VCLK cycles occur at VOE = HIGH, the FIFO register is unchanged, but the outputs VRO31 to VRO0 remain in 3-state position ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) line n line n handbook, full pagewidth active internal signal video last half-full request for line n HFL 64LLC INCADR (1) Pulse only at interlace scan. handbook, full pagewidth line qualifier LNQ VS VGT 1996 Nov 04 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth SET SCALING ACTIVE IN CONTROL STAGE 1996 Nov 04 EXTERNAL RESET, VPE = 0 no VERTICAL SYNC DETECTED yes COEFFICIENT UPDATE no VPE = 1 yes DO VERTICAL RESET yes VERTICAL SYNC DETECTED no CURRENT yes ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 7.4.11 F IELD PROCESSING The phase of the field sequence (odd/even dependent on inputs HREF and VS) is detected by means of the falling edge of VS. The current field phase is reported in the status byte by bit OEF (see Table 14). Bit OEF can be ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 8 PROGRAMMING MODEL 2 8.1 I C-bus format (1) (2) S SLAVE ADDRESS Notes 1. START condition 0100 000X (I CSA = LOW) or 0100 001X ( order to write (the circuit is slave receiver order to read (the circuit is slave transmitter)]. 3. Acknowledge, generated by the slave. ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 2 8.2 I C-bus status information 2 Table 14 I C-bus status byte (X in address byte = 1; 41H at I FUNCTION Status byte 0 (transmitted after RES = SSTB = 0) Status byte 1 (transmitted at SSTB = 1) Table 15 Function of status bits; note 1 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 8.3 Decoder part 2 Table 16 I C-bus decoder control; subaddress and data bytes for writing (X in address byte = 0; 40H 42H at I CSA = HIGH) FUNCTION SUBADDRESS Increment delay 00 H-sync begin H-sync stop H-clamp begin ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 17 Function of the register bits of Table 16 for subaddresses ‘00’ to ‘19’ SUBADDRESS IDEL7 to IDEL0 Increment delay time (dependent on application), step size = 4/LLC. The delay time is ‘00’ selectable from 4/LLC ( 1 decimal multiplier) to 1024/LLC ( 256 decimal multiplier) equals data FFH to 00H ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SUBADDRESS CKTQ4 to CKTQ0 Colour-killer threshold QAM (PAL, NTSC) from approximately equals data ‘08’ bytes F8H to 07H. CKTS4 to CKTS0 Colour-killer threshold SECAM from approximately equals data bytes ‘09’ F8H to 07H. ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SUBADDRESS CHRS S-VHS bit (chrominance from CVBS or from chrominance input) ‘0E’ controlled by bit BYPS (subaddress 06 chrominance from chrominance input CHR7 to CHR0 GPSW2 and GPSW1 general purpose switches; see Table 22 ‘ ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SUBADDRESS HC6S7 to HC6S0 Horizontal clamp stop for 60 Hz, step size = 2/LLC. The delay time is selectable from ‘17’ 254/LLC (+127 decimal multiplier) to +256/LLC ( 128 decimal multiplier) equals data 7FH to 80H. ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 21 Automatic gain control (AGC filter) LFIS1 Table 22 General purpose switches GPSW2 (PIN 32 Table 23 Luminance delay compensation YDEL2 Note 1. Step size = 2/LCC = 67.8 ns for 50 Hz and 81.5 ns for 60 Hz. 1996 Nov 04 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 24 Vertical noise reduction VNOI1 Table 25 Chrominance gain control; note Note 1. Default programmed values dependent on application. 1996 Nov 04 BIT VNOI0 BIT Product specification SAA7196 MODE normal searching window free-running mode ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 26 Chrominance saturation control for VRAM port Table 27 Luminance contrast control for VRAM port Table 28 Luminance brightness control for VRAM port 1996 Nov 04 BIT BIT BIT Product specification SAA7196 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, halfpage The tresholds are related to the 13-bit word width in the luminance processing part and influence the 1LSB to 3LSB (Y0 to Y2) with respect to the 8-bit luminance output). (1) CORI1 = 1; CORI0 = 1 (2) CORI1 = 1; CORI0 = 0 (3) CORI1 = 0 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 18 handbook, full pagewidth V Y (dB (1) 43H. (2) 53H. Fig.19 Luminance control in 50 Hz/CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; maximum aperture band-pass filter characteristic. 18 handbook, full pagewidth V Y (dB) ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 18 handbook, full pagewidth V Y (dB) ( (1) 00H. (2) 03H. Fig.21 Luminance control in 50 Hz/CVBS mode controllable by subaddress byte 06; pre-filter off and coring off; maximum aperture band-pass filter characteristic. 18 handbook, full pagewidth V Y (4) ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 18 handbook, full pagewidth V Y (dB) ( (1) 40H. (2) 41H. Fig.23 Luminance control in 60 Hz/CVBS mode controllable by subaddress byte 06; pre-filter on and coring off; other aperture band-pass filter characteristics. 18 handbook, full pagewidth V Y (dB) ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 18 handbook, halfpage V Y (dB ( (1) 80H. (2) 81H. (3) 82H. Fig.25 Luminance control in 50 Hz/S-VHS mode controllable by subaddress byte 06; pre-filter off and coring off; different aperture band-pass filter characteristics. 18 handbook, halfpage V Y (dB) ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 8.4 Scaler part 2 Table 29 I C-bus scaler control; subaddress and data bytes for writing FUNCTION SUBADDRESS Formats and sequence (2) Output data pixel/line (2) Input data pixel/line (2) Horizontal window start Horizontal filter (3) Output data lines/fi ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 30 Function of the register bits of Table 29 for subaddresses ‘20’ to ‘30’ SUBADDRESS RTB ROM table bypass switch ‘20’ anti-gamma ROM active 1 = table is bypassed OF1 to OF0 set output field mode; see Table 31 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) VC8 to VC0 vertical bypass count, sets length of bypass region (straight binary) ‘29 and 2B’ 0 0000 0000; 0 line length 1 1111 1111; 511 lines length (maximum = number of lines/field POE polarity, internally detected odd/even flag O/E ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) QPP pixel qualifier polarity fl PXQ is active-LOW (pin 51 PXQ is active-HIGH TTR transparent data transfer 0 = normal operation (VRAM data burst transfer FIFO register transparent EFE extended formats enable bit (see FS bits in subaddress ‘20’ 32-bit long word output formats 1 = extended output formats (‘ ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) Table 34 FIFO output register format select (bit EFE; see ‘30’) EFE FS1 FS0 Table 35 Horizontal decimation filter HF2 HF1 HF0 Table 36 Vertical luminance data processing VP1 VP0 0 0 bypassed ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 10 handbook, full pagewidth (dB 0.1 (1) 000. (2) 001. (3) 010. Fig.29 Horizontal frequency characteristic of luminance signal (Y) dependent on HF2 to HF0 bits (subaddress 24). 10 handbook, full pagewidth (dB 0.05 (1) 000. (2) 001. (3) 010. Fig.30 Horizontal frequency characteristic of chrominance signals (UV) without UV interpolation dependent on HF2 to HF0 bits (subaddresses 24) ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER V supply voltage; pins 14, 27, 31, 45, 61, 77 and 106 V voltage on all input/output pins I V electrostatic handling for all pins ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SYMBOL PARAMETER 2 I C-bus, SDA and SCL (pins 3 and 4) V LOW level input voltage IL V HIGH level input voltage IH I input current 3,4 I output current on pin 3 ACK V output voltage at acknowledge OL Clock input timing (LLCB) ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SYMBOL PARAMETER Horizontal PLL f nominal line frequency permissible static deviation H/ Hn Subcarrier PLL f nominal subcarrier frequency SCn f lock-in range SC Crystal oscillator; see Fig.34 and note 5 f nominal frequency permissible deviation f ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SYMBOL PARAMETER t VRO disable time to 3-state D t VRO enable time from 3-state E Response times to HFL flag t HFL rising edge to VRAM port HFL VOE enable t HFL rising edge to VCLK burst HFL VCLK Notes 1 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth VOE VCLK HD3 not valid output VRO( HD3 output HFL (1) Related to VCLK (HFL). 1996 Nov 04 t VCLK (1) (1) Fig.31 Data output timing (VCLK). 62 Product specification SAA7196 2 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth clock input LLCB data input YUV, HREF, VS input CREFB control input DIR data and control output data output YUV-bus (to 3-state clock output LLCB output CREFB 1996 Nov 04 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth clock input LLC data input CVBS, CHR handbook, full pagewidth 26.8 MHz (3rd harmonic 20%) a. Oscillator application. (1) Value depends on crystal parameters. 1996 Nov 04 t LLC t LLCH t SU ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 11 PROCESSING DELAYS Table 37 Processing delays of signals PORTS CVBS/CHR to YUV YUV to VRO CVBS/CHR to VRO 1996 Nov 04 DELAY IN LLC/LLCB CYCLES 216 56 in YUV mode 58 in RGB mode 272 in YUV mode 274 in RGB modes 65 Product specifi ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 12 APPLICATION INFORMATION 1996 Nov 04 66 Product specification SAA7196 pagewidth full handbook, ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) handbook, full pagewidth SDA SCL IICSA V DDD1 to V DDD7 0 SSD each supply has its own decoupling digital capacitor 8 CHR7 to CHR0 CVBS7 to CVBS0 8 HSY HCL RTCO RTS1 RTS0 CGCE 5 V BTST ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 12.1 Programming example Coefficients to set operation for application circuits Figs 35 and 36. Slave address byte is 40H at pin 5 connected to V (or 42H at pin 5 connected to V DDD Table 38 Programming examples SUBADDRESS 00 IDEL7 to IDEL0 01 HSYB7 to HSYB0 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) SUBADDRESS 23 XO7 to XO0 24 HF2 to HF0, XO8, XS8 and XS9, XD8 and XD9 25 YD7 to YD0 26 YS7 to YS0 27 YO7 to YO0 28 AFS, VP1 and VP0, YO8, YS8 and YS9, YD8 and YD9 29 VS7 to VS0 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 13 PACKAGE OUTLINE QFP120: plastic quad flat package; 120 leads (lead length 1.95 mm); body 3.4 mm; high stand-off height pin 1 index 120 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.40 3.70 mm 3.95 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 14 SOLDERING 14.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 15 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 1996 Nov 04 NOTES 73 Product specification SAA7196 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 1996 Nov 04 NOTES 74 Product specification SAA7196 ...
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... Philips Semiconductors Digital video decoder, Scaler and Clock generator circuit (DESCPro) 1996 Nov 04 NOTES 75 Product specification SAA7196 ...
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... Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. + 24825 © Philips Electronics N.V. 1996 All rights are reserved ...